python七段数码管显示字母代码_七段数码管学号显示 vhdl

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity xuehao is

port(clk:in std_logic;

k:out std_logic_vector(7 downto 0);

smgout:out std_logic_vector(7 downto 0));

end xuehao;

architecture str of xuehao is

signal kct:integer range 0 to 7;

signal en:std_logic;

function smg(xh:integer range 0 to 9)

return std_logic_vector is

variable

smg7:std_logic_vector(7 downto 0);

begin

case xh is

WHEN 0 => smg7:="00111111";

WHEN 1 => smg7:="00000110";

WHEN 2 => smg7:="01011011";

WHEN 3 => smg7:="01001111";

WHEN 4 => smg7:="01100110";

WHEN 5 => smg7:="01101101";

WHEN 6 => smg7:="01111101";

WHEN 7 => smg7:="00000111";

WHEN 8 => smg7:="01111111";

WHEN 9 => smg7:="01101111";

end case;

return smg7;

end smg;

begin

process(clk)

variable clkct:std_logic_vector(13 downto 0);

begin

if clk'event and clk='1' then

if clkct<10000 then

clkct:=clkct+'1';

en<='0';

else

clkct:=(others=>'0');

en<='1';

end if;

end if;

end process;

process(en)