数字电路第五次实验

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY BICNT6BIT IS
PORT(
		CLR,UPDN,CLK,EN:IN STD_LOGIC;
		QF,QE,QD,QC,QB,QA:OUT STD_LOGIC
);
END BICNT6BIT;

ARCHITECTURE RTL OF BICNT6BIT IS
SIGNAL CNT:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
	QF<=CNT(5);
	QE<=CNT(4);
	QD<=CNT(3);
	QC<=CNT(2);
	QB<=CNT(1);
	QA<=CNT(0);
PROCESS(CLK,CLR)
BEGIN
	IF CLR='1' THEN CNT<="000000";
	ELSIF CLK'EVENT AND CLK='1' THEN
		IF EN='0' THEN CNT<=CNT;
		ELSE
			IF UPDN='1' THEN CNT<=CNT + '1';
			ELSE CNT<=CNT - '1';
			END IF;
		END IF;
	END IF;