用vhdl语言使用lpm来搭建一个补码乘法器,编译错误,高手帮忙0
--mul.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
library altera;
use altera.maxplus2.all;
entity mul is
port( atb,btb:in std_logic_vector(8 downto 1);
outtb:out std_logic_vector(8 downto 1)
);
end mul;
architecture a of mul is
COMPONENT lpm_mult
GENERIC (LPM_WIDTHA: POSITIVE;
LPM_WIDTHB: POSITIVE;
LPM_WIDTHS: NATURAL := 0;
LPM_WIDTHP: POSITIVE;
LPM_REPRESENTATION: STRING;
LPM_PIPELINE: INTEGER := 0;
LPM_TYPE: STRING := "LPM_MULT";
LPM_HINT: STRING := "UNUSED");
PORT (dataa: IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab: IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
aclr, clock: IN STD_LOGIC := '0';
clken: IN STD_LOGIC := '1';
sum: IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0');
result: OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0));
END COMPONENT;
begin
m:lpm_mult
generic map(LPM_REPRESENTATION=>"signed",
LPM_WIDTHA=>8,
LPM_WIDTHB=>8,lpm_widthp=>16,
lpm_widths=>16
);
port map(dataa=>atb,datab=>btb,result(15 downto 8)=>outtb(8 downto 1));
end a;
maxplusii中编译报错
错误我拷贝不出来..请高手帮忙看一看哪里错误,谢谢