【FPGA混动】基于FPGA的混沌系统开发

1.软件版本

MATLAB2013b，quartusii12.1

2.本算法理论知识

在本系统中，我们使用的混动公式如下所示：

3.部分核心代码 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY DELAY2 IS 
PORT( clk   : IN  STD_LOGIC;
 	  clear : IN  STD_LOGIC;
      Dx    : in signed          (27 DOWNTO 0);
      Dy    : in signed          (27 DOWNTO 0);
      Dz    : in signed          (27 DOWNTO 0);
	  Doutx : OUT SIGNED         (27 DOWNTO 0); 
	  Douty : OUT SIGNED         (27 DOWNTO 0); 
	  Doutz : OUT SIGNED         (27 DOWNTO 0) 
	  ); 
	  
END DELAY2; 

ARCHITECTURE a OF DELAY2 IS 
BEGIN 
  PROCESS(clk,clear) 
    BEGIN 
	  IF clear='0' THEN
		 Doutx<="0000000000100000110001000000";
		 Douty<="0000000000000110100011010000";
		 Doutz<="0000000000111010111110110000";		 		 
	  ELSIF clear='1' THEN
	    IF(clk'EVENT AND clk='1') THEN
		 Doutx<=Dx;
		 Douty<=Dy;
		 Doutz<=Dz;			  
	    END IF; 
	  END IF; 
  END PROCESS; 
END a; 

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY mult_0872b00 IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (55 DOWNTO 0)
	);
END mult_0872b00;


ARCHITECTURE SYN OF mult_0872b00 IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (55 DOWNTO 0);
	SIGNAL sub_wire1_bv	: BIT_VECTOR (27 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (27 DOWNTO 0);



	COMPONENT lpm_mult
	GENERIC (
		lpm_hint		: STRING;
		lpm_representation		: STRING;
		lpm_type		: STRING;
		lpm_widtha		: NATURAL;
		lpm_widthb		: NATURAL;
		lpm_widthp		: NATURAL
	);
	PORT (
			dataa	: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
			datab	: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
			result	: OUT STD_LOGIC_VECTOR (55 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	sub_wire1_bv(27 DOWNTO 0) <= "0000100001110010101100000000";
	sub_wire1    <= To_stdlogicvector(sub_wire1_bv);
	result    <= sub_wire0(55 DOWNTO 0);

	lpm_mult_component : lpm_mult
	GENERIC MAP (
		lpm_hint => "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
		lpm_representation => "SIGNED",
		lpm_type => "LPM_MULT",
		lpm_widtha => 28,
		lpm_widthb => 28,
		lpm_widthp => 56
	)
	PORT MAP (
		dataa => dataa,
		datab => sub_wire1,
		result => sub_wire0
	);



END SYN;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY mult_0ff3b64 IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (55 DOWNTO 0)
	);
END mult_0ff3b64;


ARCHITECTURE SYN OF mult_0ff3b64 IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (55 DOWNTO 0);
	SIGNAL sub_wire1_bv	: BIT_VECTOR (27 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (27 DOWNTO 0);



	COMPONENT lpm_mult
	GENERIC (
		lpm_hint		: STRING;
		lpm_representation		: STRING;
		lpm_type		: STRING;
		lpm_widtha		: NATURAL;
		lpm_widthb		: NATURAL;
		lpm_widthp		: NATURAL
	);
	PORT (
			dataa	: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
			datab	: IN STD_LOGIC_VECTOR (27 DOWNTO 0);
			result	: OUT STD_LOGIC_VECTOR (55 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	sub_wire1_bv(27 DOWNTO 0) <= "0000111111110011101101100100";
	sub_wire1    <= To_stdlogicvector(sub_wire1_bv);
	result    <= sub_wire0(55 DOWNTO 0);

	lpm_mult_component : lpm_mult
	GENERIC MAP (
		lpm_hint => "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
		lpm_representation => "SIGNED",
		lpm_type => "LPM_MULT",
		lpm_widtha => 28,
		lpm_widthb => 28,
		lpm_widthp => 56
	)
	PORT MAP (
		dataa => dataa,
		datab => sub_wire1,
		result => sub_wire0
	);



END SYN;

4.操作步骤与仿真结论

 

5.参考文献

[1]谢国波, 陈平华, 蔡兆波. 一种二次三项式通用FPGA混沌产生器设计[J]. 微计算机信息, 2009, 25(008):215-217.A07-05