fifo的rdata_同步Fifo和异步fifo

这一种设计的FIFO，是基于触发器的。宽度，深度的扩展更加方便，结构化跟强。以下代码在modelsim中验证过。

modulefifo_cell(sys_clk,sys_rst_n,read_fifo,write_fifo,fifo_input_data,

next_cell_data,next_cell_full,last_cell_full,cell_data_out,cell_full);

parameterWIDTH=8;

parameterD=2;

inputsys_clk;

inputsys_rst_n;

inputread_fifo,write_fifo;

input[WIDTH-1:0]fifo_input_data;

input[WIDTH-1:0]next_cell_data;

inputnext_cell_full,last_cell_full;

output[WIDTH-1:0]cell_data_out;

outputcell_full;

reg[WIDTH-1:0]cell_data_reg_array;

reg[WIDTH-1:0]cell_data_ld;

regcell_data_ld_en;

regcell_full;

regcell_full_next;

assigncell_data_out=cell_data_reg_array;

always@(posedgesys_clkornegedgesys_rst_n)

if(!sys_rst_n)

cell_full<=#D0;

elseif(read_fifo||write_fifo)

cell_full<=#Dcell_full_next;

always@(write_fifoorread_fifoornext_cell_fullorlast_cell_fullorcell_full)

casex({read_fifo,write_fifo})

2'b00:cell_full_next=cell_full;

2'b01:cell_full_next=next_cell_full;

2'b10:cell_full_next=last_cell_full;

2'b11:cell_full_next=cell_full;

endcase

always@(posedgesys_clkornegedgesys_rst_n)

if(!sys_rst_n)

cell_data_reg_array[WIDTH-1:0]<=#D0;

elseif(cell_data_ld_en)

cell_data_reg_array[WIDTH-1:0]<=#Dcell_data_ld[WIDTH-1:0];

always@(write_fifoorread_fifoorcell_fullorlast_cell_full)

casex({write_fifo,read_fifo,cell_full,last_cell_full})

4'bx1_xx:cell_data_ld_en=1'b1;

4'b10_01:cell_data_ld_en=1'b1;

default:cell_data_ld_en=1'b0;

endcase

always@(write_fifoorread_fifoornext_cell_fullorcell_fullorlast_cell_fullorfifo_input_dataornext_cell_data)

casex({write_fifo,read_fifo,next_cell_full,cell_full,last_cell_full})

5'b10_x01:cell_data_ld[WIDTH-1:0]=fifo_input_data[WIDTH-1:0];

5'b11_01x:cell_data_ld[WIDTH-1:0]=fifo_input_data[WIDTH-1:0];

default:cell_data_ld[WIDTH-1:0]=next_cell_data[WIDTH-1:0];

endcase

endmodule

modulefifo_4cell(sys_clk,sys_rst_n,fifo_input_data,write_fifo,fifo_out_data,

read_fifo,full_cell0,full_cell1,full_cell2,full_cell3);

parameterWIDTH=8;

parameterD=2;

inputsys_clk;

inputsys_rst_n;

input[WIDTH-1:0]fifo_input_data;

output[WIDTH-1:0]fifo_out_data;

inputread_fifo,write_fifo;

outputfull_cell0,full_cell1,full_cell2,full_cell3;

wire[WIDTH-1:0]dara_out_cell0,data_out_cell1,data_out_cell2,

data_out_cell3,data_out_cell4;

wirefull_cell4;

fifo_cell#(WIDTH,D)cell0

(.sys_clk(sys_clk),</