题目:设计一个2-4译码器。
module Decode_2_4(
input [1:0] indata,
input enable_n,
//output reg [3:0] outdata
output [3:0] outdata
);
/*
always @(*)begin
if(enable_n == 1'b1)
outdata = 4'b1111;
else begin
case(indata)
2'b00: outdata = 4'b1110;
2'b01: outdata = 4'b1101;
2'b10: outdata = 4'b1011;
2'b11: outdata = 4'b0111;
endcase
end
end
*/
assign outdata[3] = ~(indata[1] & indata[0] & ~enable_n);
assign outdata[2] = ~(indata[1] & ~indata[0] & ~enable_n);
assign outdata[1] = ~(~indata[1] & indata[0] & ~enable_n);
assign outdata[0] = ~(~indata[1] & ~indata[0] & ~enable_n);
endmodule