PCIE3.0 layout

PCIE3.0 的收发数据差分对走85ohm阻抗，差分对内匹配长度5mil，差分对之间匹配长度应该是1inch,当然不包括时钟对。
英文原文：route as 85ohm differential pairs,traces within a pair must be matched within 5 mils,pair to pair trace lengths should be matched within 1inch with exception of PEIE reference clock.
当前国产主控项目所做的设计如图：10层，1.8mm板厚