解帧器

STM解帧器代码
module jiezhen_stm1
(dtin,clk,dtout,reset
);
input dtin;
input clk,reset;
output [7:0] dtout;
reg flag;
reg [1:0] cnt ,state;
reg [2:0] cnt_bit;
reg [8:0] cnt_tier;
reg [3:0] cnt_row;
reg [7:0] pbuf;
reg [31:0] sp;
wire temp;
assign dtout=pbuf;
assign temp = cnt_bit[2]&cnt_bit[1]&cnt_bit[0];
always@(posedge clk or posedge reset)
if(reset)
begin
cnt <= 0;
sp <= 32’hf6f62828;
state <=2’b00;
cnt_bit <=3’b0;
cnt_tier <=9’b0;
cnt_row <=4’b0;
flag <=0;
end
else if((state2’b00)&(sp32’hf6f62828))
begin
cnt_bit <=3’b000;
cnt_tier <=9’b000000101;
cnt_row <=4’b0000;
state <=2’b01;
flag <=1’b1;
sp[31:0] <={sp[30:0],dtin};
end
else
begin
cnt_bit<=cnt_bit+1;
sp[31:0] <={sp[30:0],dtin};
if(temp)
begin
if(cnt_tier269)
begin
cnt_tier<=0;
if(cnt_row4’b1000)
cnt_row<=0;
else
cnt_row<=cnt_row+1;
end
else
cnt_tier<=cnt_tier+1;
pbuf[7:0]<=sp[7:0];
end

	 end

always@(posedge clk)
if(temp&~(state2’b00))
case(state)
2’b01:
begin
if((cnt_row4’b0000)&(cnt_tier9’b000_000_000)&~(sp[7:0]8’hf6))
state<=2’b00;
else if((cnt_row4’b0000)&(cnt_tier9’b000_000_101))
begin
if(flag)
flag=0;
else if(sp[7:0]8’h28)
state <= 2’b10;
else
state <= 2’b00;
end
end
2’b10:
begin
if ((cnt_row4’b0)&(cnt_tier9’b000_000_100)&(sp32’hf6f62828))
begin
state <= 2’b11;
cnt <=0;
end
end
2’b11:
begin
if((cnt_row4’b0000)&(cnt_tier9’b000_000_100))
begin
if(sp32’hf6f62828)
state<=2’b10;
else if(cnt2’b11)
state<=2’b00;
else
cnt<=cnt+1;
end
end
endcase
endmodule

代码有bug
WARNING:HDLCompiler:413 - “D:\lianxi\jiezhen\jiezhen_stm1\jiezhen_stm1.v” Line 61: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - “D:\lianxi\jiezhen\jiezhen_stm1\jiezhen_stm1.v” Line 71: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - “D:\lianxi\jiezhen\jiezhen_stm1\jiezhen_stm1.v” Line 74: Result of 10-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - “D:\lianxi\jiezhen\jiezhen_stm1\jiezhen_stm1.v” Line 113: Result of 3-bit expression is truncated to fit in 2-bit target.
ERROR:HDLCompiler:1401 - “D:\lianxi\jiezhen\jiezhen_stm1\jiezhen_stm1.v” Line 50: Signal flag in unit jiezhen_stm1 is connected to following multiple drivers:
Driver 0: output signal flag of instance Flip-Flop (flag).
Driver 1: output signal flag of instance Flip-Flop (_i000064).
ERROR:HDLCompiler:1401 - “D:\lianxi\jiezhen\jiezhen_stm1\jiezhen_stm1.v” Line 39: Signal cnt[1] in unit jiezhen_stm1 is connected to following multiple drivers:
请教如何解决呢？