ISE14.7常见警告及处理方法

**Xst:2677 - Node <data_rx_r0> of sequential type is unconnected in block <uart_rx_sync>.**

检查信号是否进行了声明，如果未声明，默认信号位宽为1bit。

**WARNING:Xst:1290 - Hierarchical block <m2> is unconnected in block <lane3>.
   It will be removed from the design.**

查看RTL视图，检查模块连线情况，根据实际情况，将被优化的线路使用指令防止被优化即可。

**WARNING:Xst:1710 - FF/Latch <cnt_8> (without init value) has a constant value of 0 in block <m50>. This FF/Latch will be trimmed during the optimization process.**

检查位宽是否有冗余，将位宽修改为当前足够的位宽即可消除该警告。

**ERROR:HDLCompiler:718 - "******" Line 1588: Port connections cannot be mixed ordered and named**

检查模块例化时，是否有缺少引号和点的情况。

**HDLCompiler:751 - "****.v" Line 33: Redeclaration of ansi port frame_head is not allowed**

检查是否有重定义的信号。

比如在module中定义了，然后在module内的其他部分又进行了定义。
module( input clk, input data_in)
wire [15:0] data_in;
endmodule
选择其一方法进行信号的完整定义即可，不要两边定义都用着。

**HDLCompiler:413 - "******" Line 334: Result of 32-bit expression is truncated to fit in 1-bit target.**

检查信号是否进行位宽定义，如果没有定义，该信号默认位宽为1，所以就会出现位宽不相符的情况。

**WARNING:Xst:1710 - FF/Latch <f2p_data_in_28> (without init value) has a constant value of 0 in block <lane10>. This FF/Latch will be trimmed during the optimization process.**

查看该信号模块，发现书写方式等没有问题，那么就有可能是与该信号相关的一些信号出现问题，导致该信号也出现问题，查看与该信号相关的信号是否正常。

**WARNING:Xst:1898 - Due to constant pushing, FF/Latch <****> is unconnected in block <lane8>.**

**WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cnt_baud_3> (without init value) has a constant value of 0 in block <m2>. This FF/Latch will be trimmed during the optimization process.**

检查该信号的第4bit是否一直为0，或者其他条件信号不满足导致该bit始终为0

**HDLCompiler：91 - “**” Signal <*> missing in the sensitivity list is added for synthsis purposes . HDL and post-synthesis simulations may differ as a result.**

检查一下，敏感列表中使用信号是否有错误。