内容
实验一:7人表决器的设计
实验二:算数逻辑单元的设计
实验三:JK触发器的设计
实验四:环形计数器的设计
实验五:顺序排列的设计
实验六:二进制除法器的设计
实验七:数字显示频率计的设计
实验八:序列检测器的设计
实验九:数字秒表的设计
实验十:自助售票机的设计
实验九:数字秒表的设计
设计一个数字秒表
①秒表读书显示分、秒、百分秒三个数字;
②具有异步复位和暂停功能;
③提交秒表计程序和测试程序,观测仿真波形,并对仿真波形做分析, 说明设计的正确性。
④采用分层次分模块的方法
//程序:
module stopwatch(input clk, input rst_n, input stop, output [5:0] minute, output [5:0] sec, output [6:0] hofs );
reg [6:0] counter100;
reg [5:0] counter60_s;
reg [5:0] counter60_m;
always@(posedge clk or negedge rst_n or posedge stop) begin
if(!rst_n)
counter100 <= 7'b0000000;
else if(stop)
counter100 <= counter100;
else if(counter100 < 7'b1100011)
counter100 <= counter100 + 1'b1;
else
counter100 <= 7'b0000000;
end
always@(posedge clk or negedge rst_n or posedge stop) begin
if(!rst_n)
counter60_s <= 6'b000000;
else if(stop)
counter60_s <= counter60_s;
else
if(counter60_s < 6'b111100)
if(counter100 == 7'b1100011)
counter60_s <= counter60_s + 1'b1;
else
counter60_s <= counter60_s;
else
counter60_s <= 6'b000000;
end
always@(posedge clk or negedge rst_n or posedge stop)
begin
if(!rst_n)
counter60_m <= 6'b000000;
else if(stop)
counter60_m <= counter60_m;
else if(counter60_m < 6'b111100)
if((counter60_s == 6'b111011)&&(counter100 == 7'b1100011))
counter60_m <= counter60_m + 1'b1;
else
counter60_m <= counter60_m ;
else
counter60_m <= 6'b000000;
end
assign hofs = counter100;
assign sec = counter60_s;
assign minute = counter60_m;
endmodule
//测试代码
`timescale 1ns / 1ns
module stopwatch_tb();
parameter CYCLE = 10;
reg clk, rst_n, stop;
wire [6:0] hofs;
wire [6:0] counter100;
wire [5:0] minute;
wire [5:0] sec;
wire [5:0] counter60_s;
wire [5:0] counter60_m;
always #(CYCLE/2) clk = ~clk;
initial begin
clk= 1'b0; rst_n= 1'b0; stop= 1'b0;
#(CYCLE*5) rst_n= 1'b1; stop= 1'b0;
#(CYCLE*120) rst_n= 1'b1; stop= 1'b1;
#(CYCLE*5) rst_n= 1'b1; stop= 1'b0;
#(CYCLE*37000) rst_n= 1'b0; stop= 1'b0;
#(CYCLE*5) rst_n= 1'b1; stop= 1'b0;
#(CYCLE*37000) rst_n= 1'b1; stop= 1'b0;
#(CYCLE*10000) $stop;
end
stopwatch U1(.clk(clk), .rst_n(rst_n), .stop(stop),
.minute(minute), .sec(sec), .hofs(hofs));
endmodule
结果分析:
首先是时、分以及秒的计数问题,对于分和秒的情况,肯定是用模60计数器;
由于分和秒计数都是60进制,因此,模60计数器模块是针对分秒计数功能的!
模60计数器的设计采用的是8421BCD码计数方式;
本设计采用分层次模块化方法,测试表明,可以显示分、秒、百分秒三个数字 ,异步复位和暂停功能正常。
实验十:自助售票机的设计
设计一个地铁自助售票机控制器
①投币只能为 1 元、5 元和 10 元;
②票价额为 2—6元整数;
③具有找零功能。
//程序:
module sell(rst_n, sel2_6, yuan1, yuan5, yuan10, money_return, ticket_out);
input rst_n, yuan1, yuan5, yuan10;
input[2:0] sel2_6;
output reg[2:0] money_return;
output reg ticket_out;
reg[2:0] number_of_yuan1;
reg[2:0] number_of_yuan5;
reg[2:0] number_of_yuan10;
wire[3:0] total_money;
assign total_money= number_of_yuan1+
5*number_of_yuan5+ 10*number_of_yuan10;
always@ (posedge yuan1 or negedge rst_n)
begin if(!rst_n) number_of_yuan1<= 3'b000;
else number_of_yuan1<= number_of_yuan1+ 1; end
always@ (posedge yuan5 or negedge rst_n)
begin if(!rst_n) number_of_yuan5<= 3'b000;
else number_of_yuan5<= number_of_yuan5+ 1; end
always@ (posedge yuan10 or negedge rst_n)
begin if(!rst_n) number_of_yuan10<= 3'b000;
else number_of_yuan10<= number_of_yuan10+ 1; end
always@ (*) begin
if(!rst_n) money_return= 3'b000;
else if(total_money>= sel2_6)
money_return= total_money- sel2_6;
else money_return= 3'b000; end
always@ (*) begin
if(!rst_n) ticket_out= 1'b0;
else if(total_money>= sel2_6)
ticket_out= 1'b1;
else ticket_out= 1'b0; end
endmodule
`timescale 1ns/ 1ps
module auto_sell_tb;
parameter cycle= 10;
reg rst_n;
reg[2:0] sel2_6;
reg yuan1, yuan5, yuan10;
wire[2:0] money_return;
wire ticket_out;
sell
u1(.rst_n(rst_n), .sel2_6(sel2_6), .yuan1(yuan1), .yuan5(yuan5), .yuan10(yuan10), .money_return(money_return), .ticket_out(ticket_out));
initial begin
rst_n= 1'b0; sel2_6= 3'd0; yuan1= 1'b0;
yuan5= 1'b0; yuan10= 1'b0;
#cycle rst_n= 1'b1; sel2_6= 3'd5; yuan10= 1'b1;
#cycle sel2_6= 3'd6; yuan1= 1'b1;
yuan5= 1'b1; yuan10= 1'b0;
#cycle sel2_6= 3'd3; yuan1= 1'b0;
yuan5= 1'b0; yuan10= 1'b1;
#cycle sel2_6= 3'd2; yuan1= 1'b0;
yuan5= 1'b1; yuan10= 1'b0;
#(cycle* 10) $stop; end
endmodule
结果分析:
输入只有三种情况,1元、5元和10元,首先计算1元、5元和10元的个数,然后计算出投入的总钱数,根据选择信号计算出找零的钱数,测试结果符合预期。