Verilog-组合电路设计

组合电路设计

3个裁判的表决电路

case语句

module design1(OUT, A, B, C);
    output OUT;
    input A, B, C;
    reg OUT;
        always @(A or B or C)
            case ({A, B, C})
                3'b000:OUT<=0;
                3'b001:OUT<=0;
                3'b010:OUT<=0;
                3'b100:OUT<=0;
                3'b011:OUT<=1;
                3'b101:OUT<=1;
                3'b110:OUT<=1;
                3'b111:OUT<=1;
            endcase
endmodule

逻辑代数方式

module design2(OUT, A, B, C);
    output OUT;
    input A, B, C;
        assign OUT = (A&B)|(B&C)|(A&C);
endmodule

结构描述方式

module test(OUT, A, B, C);
    output OUT;
    input A, B, C;
        and U1 (w1, A, B);
        and U2 (w2, B, C);
        and U3 (w3, A, C);
        or U4 (OUT, w1, w2, w3);
endmodule

抽象描述方式

module design4(OUT, A, B, C);
    output OUT;
    input A, B, C;
    wire [1:0] sum;
    reg OUT;
        assign sum = A+B+C;
            always @(sum)
                if(sum>1) OUT = 1;
                else OUT = 0;
endmodule

数字加法器

真值表

A	B	C_IN	SUM	C_OUT
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

代数逻辑表示为

SUM = A⊕B⊕C_IN

C_OUT = AB + (A⊕B)C_IN 

/*连续赋值*/
module one_bit_fuiladder(SUM, C_OUT, A, B, C_IN);
    input A, B, C_IN;
    output SUM, C_OUT;
        assign SUM = (A^B)^C_IN;
        assign C_OUT = (A&B)|((A^B)&C_IN);
endmodule


/*行为级*/
module one_bit_fulladder(SUM, C_OUT, A, B, C_IN);
    output SUM, C_OUT;
    input A, B, C_IN;
        assign {C_OUT, SUM} = A+B+C_IN;
endmodule

4位超前进位加法器

C1 = G0 + P0C0

C2 = G1| + P1G0 + P1P0C0

C3 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

module four_bits_fast_addder (sum_out, c_out, a, b, c_in);
    input [3:0] a, b; //加数，被加数
    input c_in; //来自前级的进位
    output [3:0] sum_out; //和
    output c_out; //进位输出
    wire [4:0] g, p, c; //产生函数、传输函数和内部进位
    assign c[0] = c_in;
    assign p = a | b;
    assign g = a & b;
    assign c[1] = g[0]|(p[0]&c[0]);
    assign c[2] = g[1]|(p[1]&(g[0] | (p[0]&c[0])));
    assign c[3] = g[2]|(p[2]&(g[1] | (p[1]&(g[0] | (p[0]&c[0])))));
    assign c[4] = g[3]|(p[3]&(g[2] | (p[2]&(g[1] | (p[1]&(g[0]|(p[0]&c[0])))))));
    assign sum_out = p^c[3:0];
    assign c_out = c[4];
endmodule

数据比较器

module four_bits_comp_1 (F, A, B, C);
    parameter comp_width = 4;
    output [2:0] F;
    input [2:0] C;
    input [comp_width-1:0] A;
    input [comp_width-1:0] B;
    reg [2:0] F;
        always @(A or B or C)
            if(A>B)         F = 3'b100;
            else if(A<B)    F = 3'b001;
            else            F = C;
endmodule

数据选择器

module mux8tol_2(d_out, d_in, sel);
    output d_out;
    input[7:0] d_in;
    input[2:0] sel;
    wire[3:0] w1;
    wire[1:0] w2;
    assign w1 = sel[0]? {d_in[7], d_in[5], d_in[3], d_in[1]}:{d_in[6], d_in[4], d_in[2], d_in[0]};
        assign w2 = sel[1]? {w1[3], w1[1]}:{w1[2], w1[0]};
        assign d_out = sel[2]? w2[1]:w2[0];
endmodule


module mux8tol(out, sel, data_in);
    output out;
    input [7:0] data_in;
    input [3:0] sel;
    reg out;
        always @ (data_in or sel)
            case (sel)
                3'b000 : out <= data_in[0];
                3'b001 : out <= data_in[1];
                3'b010 : out <= data_in[2];
                3'b011 : out <= data_in[3];
                3'b100 : out <= data_in[4];
                3'b101 : out <= data_in[5];
                3'b110 : out <= data_in[6];
                3'b111 : out <= data_in[7];
            endcase
endmodule

数字编码器

module code_8to3(F, I);
    output [2:0] F;
    input [7:0] I;
    reg [2:0] F;
        always @ (I)
            case (I)
                8'b00000000:F = 3'b000;
                8'b00000010:F = 3'b001;
                8'b00000100:F = 3'b010;
                8'b00001000:F = 3'b011;
                8'b00010000:F = 3'b100;
                8'b00100000:F = 3'b101;
                8'b01000000:F = 3'b110;
                8'b10000000:F = 3'b111;
                default: F = 3'bx;
            endcase
endmodule

8线-3线优先编码器

module mux8to3_p(data_out, Ys, Yex, sel, data_in);
    output [2:0] data_out;
    output Ys, Yex;
    input [7:0] data_in;
    input sel;
    reg [2:0] data_out;
    reg Ys, Yex;
        always @ (data_in or sel)
            if (sel) {data_out, Ys, Yex} = {3'b111, 1'b1, 1'b1};
            else
                begin
                    casex (data_in)
                        8'b0???????: {data_out, Ys, Yex} = {3'b000, 1'b1, 1'b0};
                        8'b10??????: {data_out, Ys, Yex} = {3'b001, 1'b1, 1'b0};
                        8'b110?????: {data_out, Ys, Yex} = {3'b010, 1'b1, 1'b0};
                        8'b1110????: {data_out, Ys, Yex} = {3'b011, 1'b1, 1'b0};
                        8'b11110???: {data_out, Ys, Yex} = {3'b100, 1'b1, 1'b0};
                        8'b111110??: {data_out, Ys, Yex} = {3'b101, 1'b1, 1'b0};
                        8'b1111110?: {data_out, Ys, Yex} = {3'b110, 1'b1, 1'b0};
                        8'b11111110: {data_out, Ys, Yex} = {3'b111, 1'b1, 1'b0};
                        8'b11111111: {data_out, Ys, Yex} = {3'b111, 1'b0, 1'b1};
                    endcase
                end
endmodule

二进制转化十进制8421BCD编码器

 逻辑表达式：

module BCD8421(data_out, data_in);
    output [3:0] data_out;
    input [8:0] data_in;
    reg [3:0] data_out;
        always @ (data_in)
            case (data_in)
                9'b000000000 : data_out = 4'b0000;
                9'b000000001 : data_out = 4'b0001;
                9'b000000010 : data_out = 4'b0010;
                9'b000000010 : data_out = 4'b0011;
                9'b000001000 : data_out = 4'b0100;
                9'b000010000 : data_out = 4'b0101;
                9'b000100000 : data_out = 4'b0110;
                9'b001000000 : data_out = 4'b0111;
                9'b010000000 : data_out = 4'b1000;
                9'b100000000 : data_out = 4'b1001;
                default : data_out = 4'b0000;
            endcase
endmodule

8421BCD十进制余3码编码器

module code_change(B_out, B_in);
    output [3:0] B_out;
    input [3:0] B_in;
        assign B_out = B_in+2'b11;
endmodule

数字译码器

2线-4线译码器

module test(Y, E, A);
    output [3:0] Y;
    input [1:0] A;
    input E;
    assign Y[0] = ~(~E&~A[1]&~A[0]);
    assign Y[1] = ~(~E&~A[1]&A[0]);
    assign Y[2] = ~(~E&A[1]&~A[0]);
    assign Y[3] = ~(~E&A[1]&A[0]);
endmodule

module test(Y, E, A);
    output [3:0] Y;
    input [1:0] A;
    input E;
    reg [3:0] Y;
        always @(E or A)
            case ({E, A})
                3'b1??: Y = 4'b0000;
                3'b000: Y = 4'b0001;
                3'b001: Y = 4'b0010;
                3'b010: Y = 4'b0100;
                3'b011: Y = 4'b1000;
                default: Y = 4'b0000;
            endcase
endmodule

奇偶校验器

module checker (Fod, Fev, b);
    output Fod, Fev;
    input [7:0] b;
        wire wl, w2, w3, w4, w5, w6;
            xor Ul (w1, b[0], b[1]);
            xor U2 (w2, b[2], b[3]);
            xor U3 (w3, b[4], b[5]);
            xor U4 (w4, b[6], b[7]);
            xor U5 (w5, wl, w2);
            xor U6 (w6, w3, w4);
            xor U7 (Fod, w5, w6);
            not U8 (Fev, Fod);
endmodule


module checker (Fod, Fev, b);
    output Fod, Fev;
    input [7:0] b;
    assign Fod = ^b;
    assign Fev = ~Fod;
endmodule