verilog分频电路

https://blog.csdn.net/zhangpeng8810/article/details/124203878
注意: ICG实现分频

二分频电路:

module div2(
input clk,
input rst_n,
output reg clk_o
);

always@(posedge clk or negedge rst_n) begin
if(rst_n)
	clk_o <= 1'b0;
else
	clk_o <= ~clk;
end

endmodule

八分频电路：

module div4(
input clk,
input rst_n,
output reg clk_o
);

reg [2:0] cnt;

always@(posedge clk or negedge rst_n) begin
if(!rst_n)
	cnt <= 3'b0;
else if(cnt == 7)
	cnt <= 3'b0;
else
	cnt <= cnt + 1;
end

always@(posedge clk or negedge rst_n) begin
if (!rst_n)
	clk_o <= 'b0;
else if(cnt < 4)
	clk_o <= 'b0;
else
	clk_o <= 'b1;
end

endmodule

50%占空比七分频电路:

module div7(
input clk,
input rst_n,
output reg clk_o
);

reg [2:0] cnt_p, cnt_n;
reg clk_p, clk_n;

always@(posedge clk or negedge rst_n) begin
if(!rst_n)
	cnt_p <= 'b0;
else if(cnt_p == 6)
	cnt_p <= 'b0;
else
	cnt_p <= cnt_p + 1;
end

always@(posedge clk or negedge rst_n) begin
if(!rst_n)
	clk_p <= 'b1;
else if(cnt_p < 3)
	clk_p <= 'b1;
else
	clk_p <= 'b0;
end


always@(negedeg clk or negedge rst_n) begin
if(!rst_n)
	cnt_n <= 'b0;
else if(cnt_n == 6)
	cnt_n <= 'b0;
else
	cnt_n <= cnt_n + 1;
end

always@(negedeg clk or negedge rst_n) begin
if(!rst_n)
	clk_n <= 'b1;
else if(cnt_n < 3)
	clk_n <= 'b1;
else
	clk_n <= 'b0;
end

assign clk_o = clk_p | clk_n;

endmodule

任意N(奇偶)分频电路：

module(
input clk,
input rst_n,
ouyput reg clk_o
);

parameter N = 6;
parameter WIDTH = 3;

reg [WIDTH-1:0] cnt_p, cnt_n;
reg clk_p,clk_n;

assign clk_o = (N==1) ? clk : N[0] ? (clk_p | clk_o) : clk_p;

/*******  clk_p  *******/
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
	cnt_p<= 'b0;
else if(cnt_p == N-1)
	cnt_p <= 'b0;
else
	cnt_p <= cnt_p + 1;
end

always@(posedge clk or negedge rst_n) begin
if(!rst_n)
	clk_p <= 'b1;
else if(cnt_p < (N>>1))
	clk_p <= 'b1;
else
	clk_p <= 'b0;
end


/*******  clk_n  *******/
always@(negedge clk or negedge rst_n) begin
if(!rst_n)
	cnt_n<= 'b0;
else if(cnt_n == N-1)
	cnt_n<= 'b0;
else
	cnt_n<= cnt_n+ 1;
end

always@(negedge clk or negedge rst_n) begin
if(!rst_n)
	clk_n <= 'b1;
else if(cnt_n < (N>>1))
	clk_n <= 'b1;
else
	clk_n <= 'b0;
end

endmoduule