基于f = 100Hz的Clock设计一个数字时钟,用Verilog实现以下功能
1、产生时、分、秒的计时
2、可通过3个按键来设置时、分、秒值
module clock(
input clk,
input rst_n,
input hour_set,
input [4:0] hour_set_value,
input minute_set,
input [5:0] minute_set_value,
input second_set,
input [5:0] second_set_value,
output reg [4:0] hour,
output reg [5:0] minute,
output reg [5:0] second
)
reg clk_1;
reg [6:0] cnt;
// get 1HZ clk
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt <= 0;
else if(cnt == 99)
cnt <= 0;
else
cnt <= cnt + 1;
end
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
clk_1 <= 0;
else if(cnt < 50)
clk_1 <= 0;
else
clk_1 <= 1;
end
always@(posedge clk_1 or negedge rst_n) begin
if(!rst_n)
second <= 0;
else begin
if(second_set)
second <= second_set_value;
else if(second == 59)
second <= 0;
else
second <= second + 1;
end
end
always@(posedge clk_1 or negedge rst_n) begin
if(!rst_n)
minute <= 0;
else begin
if(minute_set)
minute <= minute_set_value;
else if( (minute==59) && (second==59) )
minute <= 0;
else if(second==59)
minute <= minute + 1;
end
end
always@(posedge clk_1 or negedge rst_n) begin
if(!rst_n)
hour <= 0;
else begin
if(hour_set)
hour <= hour_set_value;
else if( (hour==23) && (minute==59) && (second==59) )
hour <= 0;
else if((minute==59) && (second==59))
hour <= hour + 1;
end
end
endmodule