HDLBits代码记录

非门

module top_module( input in, output out );
	assign out=~in;
endmodule

andgate与门

module top_module( 
    input a, 
    input b, 
    output out );
	assign out=a&&b;
endmodule

norgate或非门

module top_module( 
    input a, 
    input b, 
    output out );
	assign out=~(a||b);
endmodule

xnorgate异或非门

module top_module( 
    input a, 
    input b, 
    output out );
	assign out = ~(a^b);
endmodule

Wire decl

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
	wire x,y,z;
    assign	x = a&&b,
          	y = c&&d,
        	z = x||y,
        	out = z,
        	out_n = ~z;
endmodule

7458

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign 	p2y = (p2a&&p2b)||(p2c&&p2d),
       	 	p1y = (p1a&&p1c&&p1b)||(p1f&&p1e&&p1d);
endmodule

vector0部分赋值

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
	assign 
        outv = vec,
        o0 = outv [0],
        o1 = outv [1],
        o2 = outv [2];
    // This is ok too: assign {o2, o1, o0} = vec;
endmodule

vector1部分赋值

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
	assign
        out_hi = in[15:8],
        out_lo = in[7:0];
endmodule

Vector2部分赋值

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    // assign out[31:24] = ...;
    assign 
        out[31:24] = in[ 7: 0],
        out[23:16] = in[15: 8],
        out[15: 8] = in[23:16],
        out[ 7: 0] = in[31:24];
endmodule

Vectorgates(归约运算符运算符和逻辑运算符)

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
	assign 
        out_or_bitwise = a|b,
        out_or_logical = a||b,
        out_not[5:3] = ~b,
        out_not[2:0] = ~a;
endmodule

Gates4按位操作符

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
	assign 
        out_and = &in,
        out_or = |in,
        out_xor = ^in;
endmodule

Vector3连接运算符{}

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    // assign { ... } = { ... };
	assign
        w = {a[4:0],b[4:2]},
        x = {b[1:0],c[4:0],d[4:4]},
        y = {d[3:0],e[4:1]},
        z = {e[0:0],f[4:0],2'b11}; 
    //{w[7:0], x[7:0], y[7:0], z[7:0]} = {a[4:0], b[4:0], c[4:0], d[4:0]};
endmodule

Vectorr倒置输出

module top_module( 
    input [7:0] in,
    output [7:0] out
);
	assign 
        out[7:0] = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule

Vector4复制运算符{ {}}

module top_module (
    input [7:0] in,
    output [31:0] out );//

    // assign out = { replicate-sign-bit , the-input };
    assign out = {
  {24{in[7]}},in};
endmodule

Vector5

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    // The output is XNOR of two vectors created by 
    // concatenating and replicating the five inputs.
    // assign out = ~{ ... } ^ { ... };
    assign out = ~{
  {5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{5{a,b,c,d,e}};
endmodule

Module模块调用

module top_module ( input a, input b, output out );
	
    mod_a U1(.in1(a),.in2(b),.out(out));        //端口名对应方式
    //mod_a U1(a,b,out);        端口位置对应方式
endmodule

Module pos(同上，端口位置对应)

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
	
    mod_a U1(out1,out2,a,b,c,d);
    
endmodule

Module name(同上，端口名对应)

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);

    mod_a U1(
        .out1(out1),
        .out2(out2),
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d)
    );
    
endmodule

Module shift移位器

module top_module ( input clk, input d, output q );
	
    wire q1,q2;
    my_dff U1(clk,d,q1);
    my_dff U2(clk,q1,q2);
    my_dff U3(clk,q2,q);
    
endmodule