`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/06/04 15:19:44
// Design Name:
// Module Name: dds_3
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
可实现正弦波,余弦波,三角波(符号位待考虑),方波,如果要调频调占空比可以把里面的关键参数改成输入信号
DDS模式选择Rasterized
module dds_3(
input clk,
input [1:0]key,//选择信号
input rst_n,
input axis_config_tvalid,
input [15:0]config_poff,config_pinc,
output reg[7:0] outdata,
output [7:0]cos_data_tdata
);
wire [7:0]sin_data_tdata;
wire m_axis_data_tvalid,m_axis_phase_tvalid,event_pinc_invalid,event_poff_invalid;
wire [15:0]m_axis_phase_tdata;
//DDS正余弦波发生模块
dds_compiler_0 dds (
.aclk(clk), // input wire aclk
.s_axis_config_tvalid(axis_config_tvalid), // input wire s_axis_config_tvalid
.s_axis_config_tdata({config_poff,config_pinc}), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
.m_axis_data_tdata({sin_data_tdata,cos_data_tdata}), // output wire [15 : 0] m_axis_data_tdata
.m_axis_phase_tvalid(m_axis_phase_tvalid), // output wire m_axis_phase_tvalid
.m_axis_phase_tdata(m_axis_phase_tdata), // output wire [15 : 0] m_axis_phase_tdata
.event_pinc_invalid(event_pinc_invalid), // output wire event_pinc_invalid
.event_poff_invalid(event_poff_invalid) // output wire event_poff_invalid
);
//方波发生模块
reg [23:0]dutydata;
wire [23:0]duty_reg;
reg [23:0]cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt<=24'b0;
end
else if(cnt==24'd499)
cnt<=24'b0;
else cnt<=cnt+1'b1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dutydata<=24'd100;
end
else if(cnt<24'd100)
dutydata<=24'd100;
else dutydata<=24'd0;
end
assign duty_reg=dutydata;
//三角波发生模块
wire [7:0]tri_reg_data;
reg [7:0]tri_data;
reg [8:0]cnt1;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt1<=9'b0;
end
else if(cnt1==9'd99)
cnt1<=9'b0;
else cnt1<=cnt1+1'b1;
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
tri_data<=8'd0;
end
else if(cnt1<9'd49)
tri_data<={1'b1,cnt1};
else
tri_data<={1'b1,9'd100-cnt1};
end
assign tri_reg_data=tri_data;//可以通过加减常数进行偏置
//选择模块
always@(posedge clk or negedge rst_n)begin
case(key)
2'b00: outdata<=sin_data_tdata;
2'b01: outdata<=cos_data_tdata;
2'b10: outdata<=duty_reg;
2'b11: outdata<=tri_reg_data;
endcase
end
endmodule
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/06/04 17:58:40
// Design Name:
// Module Name: dds_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module dds_tb(
);
reg clk;
reg [1:0]key;
reg rst_n;
reg axis_config_tvalid;
reg [15:0]config_poff,config_pinc;
wire [7:0] outdata;
wire[7:0]cos_data_tdata;
dds_3 u1(.clk(clk),.rst_n(rst_n),.key(key),.axis_config_tvalid(axis_config_tvalid),.config_poff(config_poff),.config_pinc(config_pinc),.outdata(outdata),.cos_data_tdata(cos_data_tdata));
initial begin
clk<=1'b0;
rst_n<=1'b0;
key<=2'b00;
axis_config_tvalid<=1'b1;
config_poff<=16'd0;
config_pinc<=16'b11001000;
#100 rst_n<=1'b1;
#5000 key<=2'b01;
#5000 key<=2'b10;
#20000 key<=2'b11;
end
always #5 clk<=~clk;
endmodule