verilog检测模块外部信号下降沿，边沿跳变设计方法

检测一个信号的下降沿时,当start_i产生一个下降沿时，flag会产生一个脉冲。

wire flag;
reg start_delay;
assign flag = ((!start_i)&&start_delay);	
always@(posedge clk)
	start_delay <= start_i;

检测上升沿

wire flag;
reg start_delay;
assign flag = (start_i&&(!start_delay));	
always@(posedge clk)
	start_delay <= start_i;