HDLBits练习-Verfication: Writing Testbenches

HDLBits练习

Verfication: Writing Testbenches

题1：Clock

module top_module ();
    reg clk;
    always begin
        clk=1'b0;
        #5 clk=1'b1;
        #5;
    end
    
    dut u0(.clk(clk));

endmodule

题2： Testbench1

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
		A=1'b0; B=1'b0;
        
        #10;A=1'b1;
        #5;B=1'b1;
        #5;A=1'b0;      
        #20;B=1'b0;
    end

endmodule

题3：AND gate

module top_module();
    reg [1:0]in;
    reg out;
    
    initial begin
        in=2'b00;
        #10;in=2'b01;
        #10;in=2'b10;
        #10;in=2'b11;
    end
    
    andgate u0(.in(in),.out(out));
endmodule

题4：Testbench2

module top_module();
	reg clk;
    reg in;
    reg [2:0]s;
    reg out;
    always begin
        clk=1'b0;
        #5 clk=1'b1;
        #5;
    end
    
    initial begin
        in=1'b0;
        #20;in=1'b1;
        #10;in=1'b0;
        #10;in=1'b1;
        #30;in=1'b0;
    end
    
    initial begin
        s=3'd2;
        #10;s=3'd6;
        #10;s=3'd2;
        #10;s=3'd7;
        #10;s=3'd0;
    end
    
    q7 u0 (.clk(clk),.in(in),.s(s),.out(out));

endmodule

题5：T flip-flop

module top_module ();
	reg clk,reset,t,q;
    
    initial begin
        reset=1;t=1;
        #10;reset=0;
    end
    
    always begin
        clk=1'b0;
        #5 clk=1'b1;
        #5;
    end
    
    tff u0(.clk(clk),.reset(reset),.t(t),.q(q));
    
endmodule