2分频电路设计
`timescale 1ns/10ps
module div_2(clk,rst,out);
input clk,rst;
output out;
reg q;
always@(posedge clk or negedge rst)
if(!rst)
q<=1'b0;
else
q<=~q;
assign out=q;
endmodule
测试程序:
module div_2_tb();
reg clk,rst;
wire out;
div_2 wt (.clk(clk), .rst(rst), .out(out));
initial
begin
rst <= 0;
#20 rst <= 1;
#100000 rst <= 0;
end
initial
begin
clk = 0;
end
always
begin
#10 clk = ~clk;
end
endmodule