转发-FPGA架构

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原文链接：https://blog.csdn.net/nnk11/article/details/78648572
一、先来一张实际图片

二、Arria 10
Altera Arria 10 GX 160是TSMC公司采用20nm技术制造。
三、Arria 10的资源
详细的参数参看https://www.altera.com.cn/content/dam/altera-www/global/en_US/pdfs/literature/pt/arria-10-product-table.pdf，这个链接对Arria10的资源参数描述的非常详细。
四、资源参数解释
（1）LE（Logic Elements）（160K）
这个就不详细说了，就是数电里面的D触发器等一系列可以用来编程最小逻辑块。包括4-输入的LUT，可编程的寄存器等等。废话不多说，看图。

 （2）System logic elements (210 K)
这里比LE多的原因看上图。
（3）ALMs（Adaptive logic modules）（61,510）
官方文档给出的定义如下：The ALM is the basic building block of logic in the architecture. Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and two registers. With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function with up to six inputs and certain seven-input functions. In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, an ALM can efficiently implement various arithmetic functions and shift registers.
看完上面的定义，结合下图：

（4）Registers（246,040）
（5）M20K memory blocks（440） && M20K memory（8,800 Kb） && MLAB（1050 Kb）
M20K有效范围：512-16K；MLAB有效范围：32-64
举个例子，比如M9K，有效范围是256-8K，容量就是9K=9*1024=9216bits：
1、the default memory depth is 8K, in which each address is capable of storing 1 bit (8K × 1)
2、If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 × 18).
（6）Variable-precision DSP Block（156） && 18 x 19 multipliers（312）
The architectural innovation in the implementation of IEEE 754 single-precision hardened floating-point DSP (digital signal processing) blocks in Arria®10 FPGAs and SoCs enable processing rates up to 1.5 TFLOPs (Tera Floating-point Operations Per Second) and power efficiency up to 40 GFLOPs/Watt.
With the three modes available for Arria® 10 DSP blocks: standard-precision fixed-point, high-precision fixed point and single-precision floating-point.
具体结构好奇者可以看下图：

 

 

（7）下面就是一些不需要解释的参数
1. Peak fixed-point performance (GMACS)（Multiply Accumulate） 343
2. Peak floating-point performance (GFLOPS) 140
3. Global clock networks 32
4. Regional clocks 8
5. Maximum LVDS channels (1.6 G) 120
6. Maximum user I/O pins 288
7. Transceiver count (17.4 Gbps） 12
8. PCIe* hardened IP blocks (Gen3 x8) 1
9. Processor Dual-core ARM Cortex-A9 MPCore processor
10. Maximum processor frequency （1.2-GHz）1.5 GHz
11. Processor cache and co-processors
L1 instruction cache (32 KB)
L1 data cache (32 KB)
Level 2 cache (512 KB) shared
FPU single and double precision
on-chip memory is updated to 256 KB