Verilog之交通信号控制电路

verilog之交通信号灯控制电路

一、题目要求

交通信号灯的控制电路，在数码管上以红黄绿三种颜色显示当前状态的剩余时间，持续时间分别为红灯30s，黄灯5s，绿灯30s。初始为红灯，依次变换为黄灯、绿灯、红灯…输入时钟为1KHz。

二、设计思路

自顶向下设计，分而治之。
模块化设计：
①输入时钟信号变化为秒时钟信号
②撰写状态机
③时间倒计时进行七段译码管输出

三、代码部分

// 将输入为1KHz的时钟clk_lk转化为1Hz
module clk_ls_gen(clk_lk,rst_n,clk_ls);//clk_lk 1KHz  clk_ls 1Hz
input clk_lk,rst_n;
output reg clk_ls;
reg [9:0] count;
initial begin
clk_ls=0;count=0;
end
always@(posedge clk_lk or negedge rst_n)
begin
	if(!rst_n)count<='d0;    
	else if(count<'d500)
	begin
		count<=count+1;
	end   
	else begin
		clk_ls<=~clk_ls;count<=0;
	end
end  
endmodule

// 将状态机模块产生的时间变换到两个七段译码管上输出
module decoder_7seg(time1,time0,data_seg1,data_seg0);
input [1:0] time1;
input [3:0] time0;
output reg [6:0] data_seg1,data_seg0;
parameter [6:0] d0=7'b1111_110,d1=7'b0110_000,d2=7'b1101_101,d3=7'b1111_001,d4=7'b0110_011,d5=7'b1011_011,d6=7'b1011_111,d7=7'b1110_000,d8=7'b1111_111,d9=7'b1111_011;
always@(*) begin
	case(time1)
	0:data_seg1<=d0;
	1:data_seg1<=d1;
	2:data_seg1<=d2;
	3:data_seg1<=d3;
	default:data_seg1<=d0;
	endcase

	case(time0)
	0:data_seg0<=d0;
	1:data_seg0<=d1;
	2:data_seg0<=d2;
	3:data_seg0<=d3;
	4:data_seg0<=d4;
	5:data_seg0<=d5;
	6:data_seg0<=d6;
	7:data_seg0<=d7;
	8:data_seg0<=d8;
	9:data_seg0<=d9;
	default:data_seg1<=d0;
	endcase
end
endmodule

// 状态机
module tf_control(clk_ls,rst_n,data_seg1,data_seg0);
input clk_ls,rst_n;
reg [1:0] time1;
reg [3:0] time0;
output [6:0] data_seg1,data_seg0;

reg [4:0] loadtime;
reg [1:0] state;
parameter red=2'b00,yellow=2'b01,green=2'b10;

initial begin
state=red;
loadtime=30;
time1='d3;time0='d0;
end
decoder_7seg decoder_7seg(.time1(time1),.time0(time0),.data_seg1(data_seg1),.data_seg0(data_seg0));
always@(posedge clk_ls or negedge rst_n)
begin
	time1<=loadtime/10;
	time0<=loadtime%10;
	if(!rst_n)state<=red;
	else begin
	case(state)
	red:
	begin
		if(loadtime==0)begin
			state<=yellow;
			loadtime<=5;
		end 
		else loadtime<=loadtime-1;
	end
	yellow:
	begin
		if(loadtime==0)begin
			state<=green;
			loadtime<=30;
		end 
		else loadtime<=loadtime-1;
	end
	green:
	begin
		if(loadtime==0)begin
			state<=red;
			loadtime<=30;
		end 
		else loadtime<=loadtime-1;
	end
	default:begin
		state<=red;
		loadtime<=30;
	end
	endcase
	end
	
	
end
endmodule

// 交通控制灯顶层调用模块，实现1KHz的时钟输入产生七段译码管的输出
module tf_control_top(clk_lk,rst_n,data_seg1,data_seg0);
  input clk_lk,rst_n;
  output [6:0] data_seg1,data_seg0;
  clk_ls_gen u1(clk_lk,rst_n,clk_ls);
  tf_control u2(clk_ls,rst_n,data_seg1,data_seg0);
endmodule

//testbench
module tf_control_top_tb;
reg clk_lk,rst_n;
wire [6:0] data_seg1,data_seg0;
tf_control_top tf_control_top(
	.clk_lk(clk_lk),
	.rst_n(rst_n),
	.data_seg1(data_seg1),
	.data_seg0(data_seg0)
);
always #500 clk_lk=~clk_lk;//1KHz的时钟输入
initial begin
	clk_lk=0;
	rst_n=0;
	#2000 rst_n=1;
end

endmodule

四、仿真结果