VHDL实现同步D触发器

异步D触发器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiyan is
port (d,clk,rst:instd_logic;
q: out std_logic);
end shiyan;
architecture Behavioral of shiyan is
begin
process (rst,clk)
begin
if (rst=‘1’) then
q<=‘0’;
elsif (clk’event and clk=‘1’) then
q<=d;
end if;
end process;
end Behavioral;