1.管脚图
2.异步复位
library ieee;
use ieee.std_logic_1164.all;
entity dffyibu is
port(d,clk,reset : in std_logic;
q,qb : out std_logic);
end dffyibu;
architecture behave of dffyibu is
begin
process(clk,reset)
begin
if(reset = '0')then
q <= '0';
qb <= '1';
elsif(clk'event and clk = '1') then
q <= d;
qb <= not d;
end if;
end process;
end behave;
3.同步复位
library ieee;
use ieee.std_logic_1164.all;
entity dfftongbu is
port(d,clk,reset : in std_logic;
q,qb : out std_logic);
end dfftongbu;
architecture behave of dfftongbu is
begin
process(clk,reset)
begin
if(clk'event and clk = '1') then
if(reset = '0') then
q <= '0';
qb <= '1';
else
q <= d;
qb <= not d;
end if;
end if;
end process;
end behave;