(vopt-7063) Failed to find ‘glbl‘ in hierarchical name 问题解决

项目场景:

使用ISE或者vivado调用modelsim/questasim进行仿真;或者不使用集成环境,单独在modelsim/questasim编译库后进行仿真


问题描述:

在仿真前已经将glbl.v编译到work库中,仿真时输入命令

vsim -voptargs=+acc work.sys_top -L unisim -L secureip -t ps -Lf unisim_ver

仿真报错:

(vopt-7063) Failed to find ‘glbl’ in hierarchical name


解决方案:

只是编译了glbl.v是不够的,还需要确保将 glbl 作为顶级设计单元加载。

在本例中,需要对命令进行修改,添加glbl模块仿真:

vsim -voptargs=+acc work.sys_top glbl -L unisim -L secureip -t ps -Lf unisim_ver

仿真成功!

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There are some simple tricks that every design engineer should know to facilitate the usage of SystemVerilog Assertions. Although this paper is not intended to be a comprehensive tutorial on SystemVerilog Assertions, it is worthwhile to give a simplified definition of a property and the concurrent assertion of a property. 1.1 What is an assertion? An assertion is basically a "statement of fact" or "claim of truth" made about a design by a design or verification engineer. An engineer will assert or "claim" that certain conditions are always true or never true about a design. If that claim can ever be proven false, then the assertion fails (the "claim" was false). Assertions essentially become active design comments, and one important methodology treats them exactly like active design comments. More on this in Section 2. A trusted colleague and formal analysis expert[1] reports that for formal analysis, describing what should never happen using "not sequence" assertions is even more important than using assertions to describe always true conditions. 1.2 What is a property? A property is basically a rule that will be asserted (enabled) to passively test a design. The property can be a simple Boolean test regarding conditions that should always hold true about the design, or it can be a sampled sequence of signals that should follow a legal and prescribed protocol. For formal analysis, a property describes the environment of the block under verification, i.e. what is legal behavior of the inputs. 1.3 Two types of SystemVerilog assertions SystemVerilog has two types of assertions: (1) Immediate assertions (2) Concurrent assertions Immediate assertions execute once and are placed inline with the code. Immediate assertions are not exceptionally useful except in a few places, which are detailed in Section 3.

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