HDMI输入采集(AXI4 FDMA数据缓存)

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winkle_Zhang

最新推荐文章于 2024-05-31 11:23:33 发布

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分类专栏： FPGA开发问题总结文章标签： fpga开发 vivado

原文链接：https://www.cnblogs.com/milianke/p/15143914.html

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软件版本：vitis2019.2(vivado2019.2)
操作系统：WIN10 64bit
硬件平台：适用XILINX A7/K7/Z7/ZU/KU系列FPGA
6.1概述
通过前文中实验的学习，相信读者已经掌握了fdma读写bram或者ddr的基本使用，本文使用米联客编写的uivbuf ip 配合uifdma ip 实现摄像头图像的多缓存方法。

本文实验目的：

1:熟悉ADV7611 HDMI输入芯片的硬件参数

2:掌握通过米联客iic控制器实现对ADV7611寄存器的配置。

3:掌握uivbuf程序设计方法

4:掌握图像处理中最常用的三缓存设计，如何实现3帧图形缓存，确保图形不撕裂

6.2ADV7611介绍
6.2.1参数概述
在这里插入图片描述
ADV7611采用先进的CMOS工艺制造，提供64引脚、10 mm × 10 mm LQFP_EP表贴封装，符合RoHS标准，是一款高质量、单输入HDMI®接收器，内置HDMI兼容型接收器，支持HDMI 1.4a规定的所有强制性3D电视格式，和最高UXGA 60 Hz、8位的分辨率。它集成一个CEC控制器，支持能力发现和控制(CDC)特性。并且提供汽车级、专业级（无HDCP）和工业级三种版本，工作温度范围为−40 ℃至+85 ℃。

具有一个音频输出端口，用于输出从HDMI流提取的音频数据。 HDMI接收器具有高级静音控制器，可消除音频输出中的外来声频噪声。

可以访问下列音频格式：

1、来自I2S 串行器的音频流（两个音频通道）

2、来自S/PDIF串行器的音频流（两个未压缩通道或N个压缩通道，例如AC3）

3、DST音频流

HDMI端口具有专用的5 V检测和热插拔(Hot Plug™)置位引脚。该HDMI接收器还集成一个均衡器，用于确保与长电缆的接口具有鲁棒的工作性能。
6.2.2ADV7611寄存器配置
ADI官方网站只给出了C代码的寄存器配置方案，我们使用FPGA配置，需要完成从C到FPGA的移植，这个比较简单，因为我们米联客前面编写的I2C控制器可以非常方便的用于寄存器的读写配置。我们这里给出配置部分的关键代码，I2C控制的代码如何编写，以及相关的介绍可以阅读FPGA部分课程关于"I2C总线控制器及读写EEPROM"这一课程内容。

有关ADV7611的寄存器配置可以阅读配套工程uisrc/06_doc路径下的技术手册。

1:uicfg7611.v
此文件里面有寄存器的配置表，以及调用米联客的i2c控制器把寄存器的配置信息写入到ADV7611,以下配置实现了ADV7611输入的视频信号以RGB888的格式输出。这里我们没有给出ADV7611每个寄存器的功能说明，读者如果觉得有必要可以自己登录ADI的官网搜索相关资料。

这里重点是看下状态机部分代码，因为这里是我们利用米联客的I2C控制器实现寄存器的配置，这个方法在FPGA里面配置HDMI芯片的寄存器，或者摄像头的寄存器，都非常使用，状态代码如下。代码中我们设置三个关键参数，iic_en/wr_cnt/ wr_data就可以完成对I2C总线设备的配置。

//state machine write one byte and then read one byte

always@(posedge clk_i) begin

if(!rst_cnt[8])begin

REG_INDEX<= 9'd0;

iic_en <= 1'b0;

wr_data <= 32'd0;

cfg_done<= 1'b0;

TS_S <= 2'd0;

end

else begin

case(TS_S)

0:if(cfg_done == 1'b0)

TS_S <= 2'd1;

1:if(!iic_busy)begin//write data

iic_en <= 1'b1;

            wr_data[7 :0] <= REG_DATA[23:16];

            wr_data[15 :8] <= REG_DATA[15: 8];

            wr_data[23:16] <= REG_DATA[7 : 0];

end

else

TS_S <= 2'd2;

2:begin

iic_en <= 1'b0;

if(!iic_busy)begin

            REG_INDEX<= REG_INDEX + 1'b1;

            TS_S <= 2'd3;

end

end

3:begin//read rtc register

if(REG_INDEX == REG_SIZE)begin

                cfg_done <= 1'b1;

            end

            TS_S     <= 2'd0;

end

endcase

end

end

以下给出完整代码：

`timescale 1ns / 1ps

//

/*

Company : Liyang Milian Electronic Technology Co., Ltd.

Brand: 米联客(milianke)

Technical forum:uisrc.com

taobao: osrc.taobao.com

Create Date: 2019/12/17

Module Name: uicfg7611

Description:

Configure the uicfg7611 register.

Copyright: Copyright (c) msxbo

Revision: 1.0

Signal description：

1) _i input

2) _o output

3) _n activ low

4) _dg debug signal

5) _r delay or register

6) _s state mechine

*/



module uicfg7611#(

parameter     CLK_DIV = 16'd499

)

(

input clk_i,

input rst_n,

output adv_scl,

inout adv_sda,

output reg cfg_done

);    

//reset counter for delay time

reg [8 :0] rst_cnt = 9'd0;

always@(posedge clk_i) begin

if(!rst_n)

rst_cnt <= 9'd0;

else if(!rst_cnt[8])

rst_cnt <= rst_cnt + 1'b1;

end

 

reg iic_en;

wire ic_busy;

reg [31:0] wr_data;

reg [1 :0] TS_S = 2'd0;

reg [8 :0] byte_cnt = 9'd0;

wire [23:0] REG_DATA;

wire [8 :0] REG_SIZE;

reg [8 :0] REG_INDEX;

//state machine write one byte and then read one byte

always@(posedge clk_i) begin

if(!rst_cnt[8])begin

REG_INDEX<= 9'd0;

iic_en <= 1'b0;

wr_data <= 32'd0;

cfg_done<= 1'b0;

TS_S <= 2'd0;

end

else begin

case(TS_S)

0:if(cfg_done == 1'b0)

TS_S <= 2'd1;

1:if(!iic_busy)begin//write data

iic_en <= 1'b1;

            wr_data[7 :0] <= REG_DATA[23:16];

            wr_data[15 :8] <= REG_DATA[15: 8];

            wr_data[23:16] <= REG_DATA[7 : 0];

end

else

TS_S <= 2'd2;

2:begin

iic_en <= 1'b0;

if(!iic_busy)begin

            REG_INDEX<= REG_INDEX + 1'b1;

            TS_S <= 2'd3;

end

end

3:begin//read rtc register

if(REG_INDEX == REG_SIZE)begin

                cfg_done <= 1'b1;

            end

            TS_S     <= 2'd0;

end

endcase

end

end

 

uii2c#

(

.WMEN_LEN(4),

.RMEN_LEN(1),

.CLK_DIV(CLK_DIV)//499 for 50M 999 for 100M

)

uii2c_inst

(

.clk_i(clk_i),

.iic_scl(adv_scl),

.iic_sda(adv_sda),

.wr_data(wr_data),

.wr_cnt(8'd3),//write data max len = 4BYTES

.rd_data(), //read not used

.rd_cnt(8'd0),//read not used

.iic_mode(1'b0),

.iic_en(iic_en),

.iic_busy(iic_busy)

);

//7611reg

ui7611reg ui7611reg_inst(.REG_SIZE(REG_SIZE),.REG_INDEX(REG_INDEX),.REG_DATA(REG_DATA));

 

endmodule

2:ui7611reg.v

`timescale 1ns / 1ps

//

/*

Company : Liyang Milian Electronic Technology Co., Ltd.

Brand: 米联客(milianke)

Technical forum:uisrc.com

taobao: osrc.taobao.com

Create Date: 2019/12/17

Module Name: ui5640reg

Description:

Configure the ui5640reg register. video format rgb 565

Copyright: Copyright (c) msxbo

Revision: 1.0

Signal description锛?

1) _i input

2) _o output

3) _n activ low

4) _dg debug signal

5) _r delay or register

6) _s state mechine

*/



module ui7611reg

(

input [8 :0] REG_INDEX,

output reg [31:0] REG_DATA,

output [8 :0] REG_SIZE

);

assign    REG_SIZE = 9'd182;

 

//-----------------------------------------------------------------

/    Config Data REG     //    

always@(*)

case(REG_INDEX)

//write Data Index

0 : REG_DATA    =    {8'h98,8'hF4, 8'h80};    //Manufacturer ID Byte - High (Read only)

1 : REG_DATA    =    {8'h98,8'hF5, 8'h7c};    //Manufacturer ID Byte - Low (Read only)

2 : REG_DATA    =     {8'h98,8'hF8, 8'h4c};    // BIT[7]-Reset all the Reg

3 : REG_DATA    =     {8'h98,8'hF9, 8'h64};    //DC offset for analog process

4 : REG_DATA    =     {8'h98,8'hFA, 8'h6c};    //COM10 : href/vsync/pclk/data reverse(Vsync H valid)

5 : REG_DATA    =     {8'h98,8'hFB, 8'h68};    //VGA :    8'h22;    QVGA :    8'h3f;

6 : REG_DATA    =     {8'h98,8'hFD, 8'h44};    //VGA :    8'ha4;    QVGA :    8'h50;

7 : REG_DATA    =    {8'h98,8'h01, 8'h05};    //VGA :    8'h07;    QVGA :    8'h03;

8 : REG_DATA    =     {8'h98,8'h00, 8'h13};    //VGA :    8'hf0;    QVGA :    8'h78;

9 : REG_DATA    =     {8'h98,8'h02, 8'hF7};    //HREF    / 8'h80

10 : REG_DATA =     {8'h98,8'h03, 8'h40};    //VGA :    8'hA0;    QVGA :    8'hF0

11 : REG_DATA =     {8'h98,8'h04, 8'h42};    //VGA :    8'hF0;    QVGA :    8'h78

12 : REG_DATA    =    {8'h98,8'h05, 8'h28};    //

13 : REG_DATA    =     {8'h98,8'h06, 8'ha7};    //

14 : REG_DATA    =     {8'h98,8'h0b, 8'h44};    //BIT[6] :    0 :VGA; 1;QVGA

15 : REG_DATA    =     {8'h98,8'h0C, 8'h42};    //

16 : REG_DATA    =     {8'h98,8'h15, 8'h80};    //

17 : REG_DATA    =     {8'h98,8'h19, 8'h8a};    //

18 : REG_DATA    =     {8'h98,8'h33, 8'h40};    //

19 : REG_DATA    =     {8'h98,8'h14, 8'h4c};    //

20 : REG_DATA    =     {8'h44,8'hba, 8'h01};    //

21 : REG_DATA    =     {8'h44,8'h7c, 8'h01};    //    

22 : REG_DATA    =     {8'h64,8'h40, 8'h81};    //DSP_Ctrl4 :00/01 : YUV or RGB; 10 : RAW8; 11 : RAW10        

23 : REG_DATA    =    {8'h68,8'h9b, 8'h03}; //ADI recommanded setting

24 : REG_DATA    =    {8'h68,8'hc1, 8'h01};    //ADI recommanded setting

25 : REG_DATA    =    {8'h68,8'hc2, 8'h01};    //ADI recommanded setting

26 : REG_DATA    =    {8'h68,8'hc3, 8'h01};    //ADI recommanded setting

27 : REG_DATA    =    {8'h68,8'hc4, 8'h01};    //ADI recommanded setting

28 : REG_DATA    =    {8'h68,8'hc5, 8'h01};    //ADI recommanded setting

29 : REG_DATA    =    {8'h68,8'hc6, 8'h01};    //ADI recommanded setting

30 : REG_DATA    =    {8'h68,8'hc7, 8'h01};    //ADI recommanded setting

31 : REG_DATA    =    {8'h68,8'hc8, 8'h01};    //ADI recommanded setting

32 : REG_DATA    =    {8'h68,8'hc9, 8'h01};    //ADI recommanded settin g

33 : REG_DATA    =    {8'h68,8'hca, 8'h01};    //ADI recommanded setting

34 : REG_DATA    =    {8'h68,8'hcb, 8'h01};    //ADI recommanded setting

35 : REG_DATA    =    {8'h68,8'hcc, 8'h01};    //ADI recommanded setting

36 : REG_DATA    =    {8'h68,8'h00, 8'h00};     //Set HDMI input Port A

37 : REG_DATA    =    {8'h68,8'h83, 8'hfe};    //terminator for Port A

38 : REG_DATA    =    {8'h68,8'h6f, 8'h08};    //ADI recommended setting

39 : REG_DATA    =    {8'h68,8'h85, 8'h1f};    //ADI recommended setting

40 : REG_DATA    =    {8'h68,8'h87, 8'h70};    //ADI recommended setting

41 : REG_DATA    =    {8'h68,8'h8d, 8'h04};    //LFG

42 : REG_DATA    =    {8'h68,8'h8e, 8'h1e};    //HFG

43 : REG_DATA    =    {8'h68,8'h1a, 8'h8a};    //unmute audio

44 : REG_DATA    =    {8'h68,8'h57, 8'hda};    // ADI recommended setting

45 : REG_DATA    =    {8'h68,8'h58, 8'h01};

46 : REG_DATA    =    {8'h68,8'h75, 8'h10};

47 : REG_DATA    =     {8'h68,8'h6c ,8'ha3};//enable manual HPA

48 : REG_DATA    =     {8'h98,8'h20 ,8'h70};//HPD low

49 : REG_DATA    =     {8'h64,8'h74 ,8'h00};//disable internal EDID

//edid

//0: REG_DATA    =     {8'h68,8'h6c ,8'ha3}; enable manual HPA

//1: REG_DATA    =     {8'h98,8'h20 ,8'h70};//HPD low

//2: REG_DATA    =     {8'h64,8'h74 ,8'h00};//disable internal EDID

//edid par

50 : REG_DATA    =     {8'h6c,8'd0 , 8'h00};

51 : REG_DATA    =     {8'h6c,8'd1 , 8'hFF};

52 : REG_DATA    =     {8'h6c,8'd2 , 8'hFF};

53 : REG_DATA    =     {8'h6c,8'd3 , 8'hFF};

54 : REG_DATA    =     {8'h6c,8'd4 , 8'hFF};

55 : REG_DATA    =     {8'h6c,8'd5 , 8'hFF};

56 : REG_DATA    =     {8'h6c,8'd6 , 8'hFF};

57 : REG_DATA    =     {8'h6c,8'd7 , 8'h00};

58 : REG_DATA    =     {8'h6c,8'd8 , 8'h20};

59 : REG_DATA    =     {8'h6c,8'd9 , 8'hA3};

60 : REG_DATA    =     {8'h6c,8'd10 , 8'h29};

61 : REG_DATA    =     {8'h6c,8'd11 , 8'h00};

62 : REG_DATA    =     {8'h6c,8'd12 , 8'h01};

63 : REG_DATA    =     {8'h6c,8'd13 , 8'h00};

64 : REG_DATA    =     {8'h6c,8'd14 , 8'h00};

65 : REG_DATA    =     {8'h6c,8'd15 , 8'h00};

66 : REG_DATA    =     {8'h6c,8'd16 , 8'h23};

67 : REG_DATA    =     {8'h6c,8'd17 , 8'h12};

68 : REG_DATA    =     {8'h6c,8'd18 , 8'h01};

69 : REG_DATA    =     {8'h6c,8'd19 , 8'h03};

70 : REG_DATA    =     {8'h6c,8'd20 , 8'h80};

71 : REG_DATA    =     {8'h6c,8'd21 , 8'h73};

72 : REG_DATA    =     {8'h6c,8'd22 , 8'h41};

73 : REG_DATA    =     {8'h6c,8'd23 , 8'h78};

74 : REG_DATA    =     {8'h6c,8'd24 , 8'h0A};

75 : REG_DATA    =     {8'h6c,8'd25 , 8'hF3};

76 : REG_DATA    =     {8'h6c,8'd26 , 8'h30};

77 : REG_DATA    =     {8'h6c,8'd27 , 8'hA7};

78 : REG_DATA    =     {8'h6c,8'd28 , 8'h54};

79 : REG_DATA    =     {8'h6c,8'd29 , 8'h42};

80 : REG_DATA    =     {8'h6c,8'd30 , 8'hAA};

81 : REG_DATA    =     {8'h6c,8'd31 , 8'h26};

82 : REG_DATA    =     {8'h6c,8'd32 , 8'h0F};

83 : REG_DATA    =     {8'h6c,8'd33 , 8'h50};

84 : REG_DATA    =     {8'h6c,8'd34 , 8'h54};

85 : REG_DATA    =     {8'h6c,8'd35 , 8'h25};

86 : REG_DATA    =     {8'h6c,8'd36 , 8'hC8};

87 : REG_DATA    =     {8'h6c,8'd37 , 8'h00};

88 : REG_DATA    =     {8'h6c,8'd38 , 8'h61};

89 : REG_DATA    =     {8'h6c,8'd39 , 8'h4F};

90 : REG_DATA    =     {8'h6c,8'd40 , 8'h01};

91 : REG_DATA    =     {8'h6c,8'd41 , 8'h01};

92 : REG_DATA    =     {8'h6c,8'd42 , 8'h01};

93 : REG_DATA    =     {8'h6c,8'd43 , 8'h01};

94 : REG_DATA    =     {8'h6c,8'd44 , 8'h01};

95 : REG_DATA    =     {8'h6c,8'd45 , 8'h01};

96 : REG_DATA    =     {8'h6c,8'd46 , 8'h01};

97 : REG_DATA    =     {8'h6c,8'd47 , 8'h01};

98 : REG_DATA    =     {8'h6c,8'd48 , 8'h01};

99 : REG_DATA    =     {8'h6c,8'd49 , 8'h01};

100 : REG_DATA    =     {8'h6c,8'd50 , 8'h01};

101 : REG_DATA    =     {8'h6c,8'd51 , 8'h01};

102 : REG_DATA    =     {8'h6c,8'd52 , 8'h01};

103 : REG_DATA    =     {8'h6c,8'd53 , 8'h01};

104 : REG_DATA    =     {8'h6c,8'd54 , 8'h02};

105 : REG_DATA    =     {8'h6c,8'd55 , 8'h3A};

106 : REG_DATA    =     {8'h6c,8'd56 , 8'h80};

107 : REG_DATA    =     {8'h6c,8'd57 , 8'h18};

108 : REG_DATA    =     {8'h6c,8'd58 , 8'h71};

109 : REG_DATA    =     {8'h6c,8'd59 , 8'h38};

110 : REG_DATA    =     {8'h6c,8'd60 , 8'h2D};

111 : REG_DATA    =     {8'h6c,8'd61 , 8'h40};

112 : REG_DATA    =     {8'h6c,8'd62 , 8'h58};

113 : REG_DATA    =     {8'h6c,8'd63 , 8'h2C};

114 : REG_DATA    =     {8'h6c,8'd64 , 8'h45};

115 : REG_DATA    =     {8'h6c,8'd65 , 8'h00};

116 : REG_DATA    =     {8'h6c,8'd66 , 8'h80};

117 : REG_DATA    =     {8'h6c,8'd67 , 8'h88};

118 : REG_DATA    =     {8'h6c,8'd68 , 8'h42};

119 : REG_DATA    =     {8'h6c,8'd69 , 8'h00};

120 : REG_DATA    =     {8'h6c,8'd70 , 8'h00};

121 : REG_DATA    =     {8'h6c,8'd71 , 8'h1E};

122 : REG_DATA    =     {8'h6c,8'd72 , 8'h8C};

123 : REG_DATA    =     {8'h6c,8'd73 , 8'h0A};

124 : REG_DATA    =     {8'h6c,8'd74 , 8'hD0};

125 : REG_DATA    =     {8'h6c,8'd75 , 8'h8A};

126 : REG_DATA    =     {8'h6c,8'd76 , 8'h20};

127 : REG_DATA    =     {8'h6c,8'd77 , 8'hE0};

128 : REG_DATA    =     {8'h6c,8'd78 , 8'h2D};

129 : REG_DATA    =     {8'h6c,8'd79 , 8'h10};

130 : REG_DATA    =     {8'h6c,8'd80 , 8'h10};

131 : REG_DATA    =     {8'h6c,8'd81 , 8'h3E};

132 : REG_DATA    =     {8'h6c,8'd82 , 8'h96};

133 : REG_DATA    =     {8'h6c,8'd83 , 8'h00};

134 : REG_DATA    =     {8'h6c,8'd84 , 8'h80};

135 : REG_DATA    =     {8'h6c,8'd85 , 8'h88};

136 : REG_DATA    =     {8'h6c,8'd86 , 8'h42};

137 : REG_DATA    =     {8'h6c,8'd87 , 8'h00};

138 : REG_DATA    =     {8'h6c,8'd88 , 8'h00};

139 : REG_DATA    =     {8'h6c,8'd89 , 8'h18};

140 : REG_DATA    =     {8'h6c,8'd90 , 8'h00};

141 : REG_DATA    =     {8'h6c,8'd91 , 8'h00};

142 : REG_DATA    =     {8'h6c,8'd92 , 8'h00};

143 : REG_DATA    =     {8'h6c,8'd93 , 8'hFC};

144 : REG_DATA    =     {8'h6c,8'd94 , 8'h00};

145 : REG_DATA    =     {8'h6c,8'd95 , 8'h48};

146 : REG_DATA    =     {8'h6c,8'd96 , 8'h44};

147 : REG_DATA    =     {8'h6c,8'd97 , 8'h4D};

148 : REG_DATA    =     {8'h6c,8'd98 , 8'h49};

149 : REG_DATA    =     {8'h6c,8'd99 , 8'h20};

150 : REG_DATA    =     {8'h6c,8'd100 , 8'h20};

151 : REG_DATA    =     {8'h6c,8'd101 , 8'h20};

152 : REG_DATA    =     {8'h6c,8'd102 , 8'h20};

153 : REG_DATA    =     {8'h6c,8'd103 , 8'h0A};

154 : REG_DATA    =     {8'h6c,8'd104 , 8'h20};

155 : REG_DATA    =     {8'h6c,8'd105 , 8'h20};

156 : REG_DATA    =     {8'h6c,8'd106 , 8'h20};

157 : REG_DATA    =     {8'h6c,8'd107 , 8'h20};

158 : REG_DATA    =     {8'h6c,8'd108 , 8'h00};

159 : REG_DATA    =     {8'h6c,8'd109 , 8'h00};

160 : REG_DATA    =     {8'h6c,8'd110 , 8'h00};

161 : REG_DATA    =     {8'h6c,8'd111 , 8'hFD};

162 : REG_DATA    =     {8'h6c,8'd112 , 8'h00};

163 : REG_DATA    =     {8'h6c,8'd113 , 8'h32};

164 : REG_DATA    =     {8'h6c,8'd114 , 8'h55};

165 : REG_DATA    =     {8'h6c,8'd115 , 8'h1F};

166 : REG_DATA    =     {8'h6c,8'd116 , 8'h45};

167 : REG_DATA    =     {8'h6c,8'd117 , 8'h0F};

168 : REG_DATA    =     {8'h6c,8'd118 , 8'h00};

169 : REG_DATA    =     {8'h6c,8'd119 , 8'h0A};

170 : REG_DATA    =     {8'h6c,8'd120 , 8'h20};

171 : REG_DATA    =     {8'h6c,8'd121 , 8'h20};

172 : REG_DATA    =     {8'h6c,8'd122 , 8'h20};

173 : REG_DATA    =     {8'h6c,8'd123 , 8'h20};

174 : REG_DATA    =     {8'h6c,8'd124 , 8'h20};

175 : REG_DATA    =     {8'h6c,8'd125 , 8'h20};

176 : REG_DATA    =     {8'h6c,8'd126 , 8'h01};

177 : REG_DATA    =     {8'h6c,8'd127 , 8'h24};

178 : REG_DATA    =     {8'h64,8'h74 , 8'h01};// enable internal EDID

179 : REG_DATA    =     {8'h98,8'h20 , 8'hf0};// HPD high

180 : REG_DATA    =     {8'h68,8'h6c , 8'ha2};// disable manual HPA    

181 : REG_DATA    = {8'h98,8'hf4 , 8'h00};

default:REG_DATA =0;

endcase

endmodule

6.3硬件电路分析
6.3.1HDMI输入
在这里插入图片描述
6.2.2HDMI输出

6.2.4fpga_pin.xdc中HDMI输入输出IO约束

#

create_clock -period 10.000 -name sysclk [get_ports sysclk]

set_property PACKAGE_PIN AA3 [get_ports sysclk]

set_property IOSTANDARD SSTL135 [get_ports sysclk]

 

#-------------HDMI IN II2C-----------------------------

set_property PACKAGE_PIN AD23 [get_ports adv_scl_0]

set_property PACKAGE_PIN AD24 [get_ports adv_sda_0]

set_property IOSTANDARD LVCMOS33 [get_ports adv_scl_0]

set_property IOSTANDARD LVCMOS33 [get_ports adv_sda_0]

 

set_property PACKAGE_PIN A13 [get_ports adv_rst]

set_property IOSTANDARD LVCMOS33 [get_ports adv_rst]

#-------------HDMI IO----------------------------------

create_clock -period 6.734 -name hdmi_clk [get_ports hdmi_in_clk]

set_property PACKAGE_PIN AA23 [get_ports hdmi_in_clk]

set_property PACKAGE_PIN AE22 [get_ports hdmi_in_active_video]

set_property PACKAGE_PIN AD21 [get_ports hdmi_in_vsync]

set_property PACKAGE_PIN W20 [get_ports {hdmi_in_data[0]}]

set_property PACKAGE_PIN AC22 [get_ports {hdmi_in_data[1]}]

set_property PACKAGE_PIN AB22 [get_ports {hdmi_in_data[2]}]

set_property PACKAGE_PIN AF25 [get_ports {hdmi_in_data[3]}]

set_property PACKAGE_PIN AF24 [get_ports {hdmi_in_data[4]}]

set_property PACKAGE_PIN AF23 [get_ports {hdmi_in_data[5]}]

set_property PACKAGE_PIN AE23 [get_ports {hdmi_in_data[6]}]

set_property PACKAGE_PIN AE21 [get_ports {hdmi_in_data[7]}]

set_property PACKAGE_PIN Y21 [get_ports {hdmi_in_data[8]}]

set_property PACKAGE_PIN AB24 [get_ports {hdmi_in_data[9]}]

set_property PACKAGE_PIN AB21 [get_ports {hdmi_in_data[10]}]

set_property PACKAGE_PIN AC21 [get_ports {hdmi_in_data[11]}]

set_property PACKAGE_PIN W23 [get_ports {hdmi_in_data[12]}]

set_property PACKAGE_PIN W24 [get_ports {hdmi_in_data[13]}]

set_property PACKAGE_PIN AD25 [get_ports {hdmi_in_data[14]}]

set_property PACKAGE_PIN AE25 [get_ports {hdmi_in_data[15]}]

set_property PACKAGE_PIN AC23 [get_ports {hdmi_in_data[16]}]

set_property PACKAGE_PIN AC24 [get_ports {hdmi_in_data[17]}]

set_property PACKAGE_PIN AD26 [get_ports {hdmi_in_data[18]}]

set_property PACKAGE_PIN AE26 [get_ports {hdmi_in_data[19]}]

set_property PACKAGE_PIN AA25 [get_ports {hdmi_in_data[20]}]

set_property PACKAGE_PIN AB25 [get_ports {hdmi_in_data[21]}]

set_property PACKAGE_PIN AB26 [get_ports {hdmi_in_data[22]}]

set_property PACKAGE_PIN AC26 [get_ports {hdmi_in_data[23]}]

 

 

set_property IOSTANDARD LVCMOS33 [get_ports hdmi_in_clk]

set_property IOSTANDARD LVCMOS33 [get_ports hdmi_in_active_video]

set_property IOSTANDARD LVCMOS33 [get_ports hdmi_in_vsync]

set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_in_data[*]}]

 

set_property PACKAGE_PIN Y23 [get_ports HDMI_TX_CLK_P]

set_property PACKAGE_PIN W25 [get_ports {HDMI_TX_P[0]}]

set_property PACKAGE_PIN Y22 [get_ports {HDMI_TX_P[1]}]

set_property PACKAGE_PIN Y25 [get_ports {HDMI_TX_P[2]}]

 

set_property IOSTANDARD TMDS_33 [get_ports HDMI_TX_CLK_P]

set_property IOSTANDARD TMDS_33 [get_ports {HDMI_TX_P[*]}]

 

set_property DCI_CASCADE {32 34} [get_iobanks 33]

 

set_property CFGBVS VCCO [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property BITSTREAM.GENERAL.COMPRESS true [current_design]

set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]

6.4硬件连线
在这里插入图片描述
6.5PL图形化设计
6.5.1系统框图

6.5.2PL图形化编程