HDLBits练习（七）移位寄存器

1.构建一个四位移位寄存器

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
	
    always@(posedge clk or posedge areset)begin
        if(areset)begin
        	q <= 4'd0;    
        end
        else if(load)begin
             q <= data;
        end
        else if(ena)begin
            q <= q >> 1;
        end
        else begin
           q <= q; 
        end
    end
        
endmodule

2.100位环形移位寄存器

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 

    always@(posedge clk)begin     
        if(load)begin
            q <= data;
    	end
        else begin
            case(ena)
                2'b01:	q <= {q[0],q[99:1]};
                2'b10:	q <= {q[98:0],q[99]};
                default: q <= q;
            endcase
    	end
    end
endmodule

3.建立一个具有同步负载的64位算术移位寄存器。移位器可以向左和向右移动1或8位的位置（由数量选择）。

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 

    always @(posedge clk)begin
        if(load)begin
           q <= data; 
        end
        else if(ena)begin
            case(amount)
                2'b00: q <= q << 1;
                2'b01: q <= q << 8;
                2'b10: q <= {q[63],q[63:1]};
                2'b11: q <= {{8{q[63]}},q[63:8]};  //算术右移时，保留最高符号位，右移八位，则最高位由8位最高位代替
            endcase
        end  
        else begin
            q <= q;
        end
    end
endmodule

4.5位Galois LFSR（线性反馈移位寄存器）

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    
    always @(posedge clk)begin
        if(reset)begin
           q <= 5'h1; 
        end
        else begin
            q <= {q[0]^1'b0,q[4],q[3]^q[0],q[2],q[1]};
        end
    end  
endmodule

5.3位LFSR

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
	
    always @(posedge KEY[0])begin
        if(KEY[1])begin
           LEDR <= SW; 
        end
        else begin
            LEDR <= {LEDR[1]^LEDR[2],LEDR[0],LEDR[2]}; 
        end       
    end

endmodule

6.32位LFSR

有关说明，请参见Lfsr5。

在位32、22、2和1处用抽头构建32位Galois LFSR。

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
	
    integer i;
    always @(posedge clk)begin
        if(reset)begin
           q <= 32'h1; 
        end
        else for(i=0;i<32;i++)begin
            if(i==0 || i == 1 || i == 21) begin
                q[i] <= q[i+1] ^ q[0];
            end
            else if(i == 31)begin
                q[31] <= q[0] ^ 1'b0;
            end
            else begin
                q[i] <= q[i+1];
            end
        end
    end      
endmodule

7.移位寄存器

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
	
    reg [3:0] q;
    
    assign out = q[0];
    always @(posedge clk)begin
        if(~resetn)begin
            q <= 4'd0;
        end
        else begin
            q <= {in,q[3],q[2],q[1]};
        end
    end
endmodule

8.n位移位寄存器

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //

	MUXDFF u0_MUXDFF(
        		 .w(KEY[3]),
                 .L(KEY[2]),
                 .E(KEY[1]),
                 .clk(KEY[0]),
        		 .R(SW[3]),
       		 	 .Q(LEDR[3])
                );
	MUXDFF u1_MUXDFF(
        		 .w(LEDR[3]),
                 .L(KEY[2]),
                 .E(KEY[1]),
                 .clk(KEY[0]),
        		 .R(SW[2]),
        		 .Q(LEDR[2])
                );
	MUXDFF u2_MUXDFF(
        		 .w(LEDR[2]),
                 .L(KEY[2]),
                 .E(KEY[1]),
                 .clk(KEY[0]),
       		 	 .R(SW[1]),
                 .Q(LEDR[1])
                );
	MUXDFF u3_MUXDFF(
        		 .w(LEDR[1]),
                 .L(KEY[2]),
                 .E(KEY[1]),
                 .clk(KEY[0]),
        		 .R(SW[0]),
        		 .Q(LEDR[0])
                );

endmodule

module MUXDFF (
    input clk,
    input w,R,E,L,
    output Q
);
    wire tmp;
    assign tmp = E ? w : Q;
    always @(posedge clk)begin
        Q <= L? R : tmp;
    end

endmodule

9.八位移位寄存器

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 

    reg [7:0] Q;
    
    always @(posedge clk)begin
        if(enable)begin
            Q <= {Q[6:0],S};
        end
        else begin
            Q <= Q;
        end
    end
    
    assign Z = Q[{A,B,C}];    {A,B,C} == 3'bxxx,与地址位等效，如3'd5需要二进制3'b101来存储

    /*
    always @(posedge clk)begin
        case({A,B,C})
            3'b000:  Z <= Q[0];
            3'b001:  Z <= Q[1];
            3'b010:  Z <= Q[2];
            3'b011:  Z <= Q[3];
            3'b100:  Z <= Q[4];
            3'b101:  Z <= Q[5];
            3'b110:  Z <= Q[6];
            3'b111:  Z <= Q[7];
        endcase
    end
*/
endmodule