HDLBits刷题（电路-锁存器与触发器）

D Filp-flop

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
    always@(posedge clk)
        q<=d;
endmodule

D Filp-flops

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
always@(posedge clk)
        q<=d;
endmodule

DFF with reset

module top_module (
    input clk,
    input reset,           
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk)begin
        if(reset) q<=8'b0;
        else q<=d;end
endmodule

DFF with reset value

复位信号，1有效。置位信号，0有效。同步：只有时钟控制。异步：复位也能控制

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always@(negedge clk)begin
        if(reset) q<=8'h34;
        else q<=d;end
endmodule

DFF with asynchronous reset

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset)begin
        if(areset) q<=8'b0;
        else q<=d;end
endmodule

DFF with byte enable

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk)begin
        if(~resetn) q<=16'b0;
        else  begin q[15:8]<=byteena[1]?d[15:8]:q[15:8];q[7:0]<=byteena[0]?d[7:0]:q[7:0];end
    end
endmodule

D latch

module top_module (
    input d, 
    input ena,
    output q);
    always@(*)
       q=ena?d:q;
endmodule

DFF

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
	always@(posedge clk or posedge ar)begin
        if(ar) q<=0;
        else q<=d;end
endmodule

DFF

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
	always@(posedge clk )begin
        if(r) q<=0;
        else q<=d;end
endmodule

DFF+gate

module top_module (
    input clk,
    input in, 
    output out);
always@(posedge clk)
       out<=in^out;
endmodule

MUX and DFF

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    always@(posedge clk)
            Q<=L?r_in:q_in;
endmodule

MUX and DFF

module top_module (
    input clk,
    input w, R, E, L,
    output reg Q
);
always@(posedge clk)
    Q<=L?R:(E?w:Q);
endmodule

DFFs and gates

module top_module (
    input clk,
    input x,
    output z
); 
    reg q1,q2,q3;
    assign z=!(q1|q2|q3);
    always@(posedge clk)begin
        q1<=x^q1;q2<=x&&(~q2);q3<=(~q3)||x;
    end
endmodule

create circuit from truth table

module top_module (
    input clk,
    input j,
    input k,
    output reg Q); 
	always@(posedge clk)begin
        case({j,k})
        	2'b00:Q<=Q;
            2'b01:Q<=1'b0;
            2'b10:Q<=1'b1;
            2'b11:Q<=!Q;
            default:Q<=Q;
        endcase
    end
endmodule

Detect on edge

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0]in_buff;
    always@(posedge clk) begin
        pedge<=(in^in_buff)&in;
        in_buff<=in;
    end
endmodule

Detect both edge

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
	reg [7:0]in_buff;
    always@(posedge clk) begin
        anyedge<=in^in_buff;
        in_buff<=in;
    end
endmodule

Edge capture register

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0]in_buff;
    always@(posedge clk) begin
        if(reset==1'b1)begin
            out<=32'b0;in_buff<=in;end
        else begin
            out<=(~in)&in_buff|out;
            in_buff<=in;
        end
    end
endmodule

Dual-edge triggered

module top_module (
    input clk,
    input d,
    output reg q
);
    reg q_up,q_down;
    always @(posedge clk )
    q_up<=d;
	always @(negedge clk)
    q_down<=d;
    assign q=clk?q_up:q_down;
endmodule