Exams/m2014 q4k

法一：

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    wire w1,w2,w3;
    //声明四个模块
    D_flip ins1(clk,in,resetn,w1);
    D_flip ins2(clk,w1,resetn,w2);
    D_flip ins3(clk,w2,resetn,w3);
    D_flip ins4(clk,w3,resetn,out);

endmodule
//声明一个D触发器
module D_flip (input clk, input D,input resetn, output Q);
    always @(posedge clk)
        begin
            if(!resetn)
                Q <= 1'b0;
            else
            	Q <= D;
        end
endmodule

法二：

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);

    wire w1,w2,w3;
    always @(posedge clk)
        begin
            if(!resetn)
                begin
                    w1 <= 1'b0;
                    w2 <= 1'b0;
                    w3 <= 1'b0;
                    out <= 1'b0;
                end
            else
                begin
                    w1 <= in;
                    w2 <= w1;
                    w3 <= w2;
                    out <= w3;
                end
        end
endmodule

参考答案：

module top_module (
	input clk,
	input resetn,
	input in,
	output out
);

	reg [3:0] sr;
	
	// Create a shift register named sr. It shifts in "in".
	always @(posedge clk) begin
		if (~resetn)		// Synchronous active-low reset
			sr <= 0;
		else 
			sr <= {sr[2:0], in};
	end
	
	assign out = sr[3];		// Output the final bit (sr[3])

endmodule