verilog的设计代码如下:
`timescale 1ns/1ns
module multi_pipe#(
parameter size = 4
)(
input clk ,
input rst_n ,
input [size-1:0] mul_a ,
input [size-1:0] mul_b ,
output reg [size*2-1:0] mul_out
);
parameter N = 2 * size;
reg [N-1:0] sum_tmp1 ;
reg [N-1:0] sum_tmp2 ;
wire [N-1:0] mul_a_extend ;
wire [N-1:0] mul_b_extend ;
wire [N-1:0] mul_result[size-1:0] ;
genvar i;
generate
for(i = 0; i < size; i = i + 1) begin:add
assign mul_result[i] = mul_b[i] ? mul_a_extend << i : 'd0;
end
endgenerate
assign mul_a_extend = {{size{1'b0}}, mul_a};
assign mul_b_extend = {{size{1'b0}}, mul_b};
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sum_tmp1 <= 'd0;
sum_tmp2 <= 'd0;
end
else begin
sum_tmp1 <= mul_result[0] + mul_result[1];
sum_tmp2 <= mul_result[2] + mul_result[3];
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
mul_out <= 'd0;
end
else begin
mul_out <= sum_tmp1 + sum_tmp2;
end
end
endmodule
testbench代码如下:
module multi_pipe_tb();
reg clk ;
reg rst_n ;
reg [3:0] mul_a ;
reg [3:0] mul_b ;
wire [7:0] mul_out ;
initial begin
clk = 1'b0;
rst_n = 1'b0;
#30
rst_n = 1'b1;
end
always #10 clk = ~clk;
initial begin
mul_a = 'd0;
mul_b = 'd0;
#120
mul_a = 'd1;
mul_b = 'd2;
#200
mul_a = 'd2;
mul_b = 'd3;
#60
$finish;
end
multi_pipe #
( 4)
u_multi_pipe(
.clk (clk) ,
.rst_n (rst_n) ,
.mul_a (mul_a),
.mul_b (mul_b),
.mul_out(mul_out)
);
initial begin
$fsdbDumpfile("multi_pipe.fsdb");
$fsdbDumpvars;
end
endmodule
仿真波形如下所示: