红外遥控（二）
一、红外采集IP自定义封装代码
这个自定义IP包含三个模块的代码，一个自己写的代码，另外两个是Xilinx封装IP的时候生成的AXI4的代码模块，生成的两个代码模块要稍微修改一下才能使用。
下面的这个是自己写的
`timescale 1ns / 1ps
//================================================//
// 实现ENC协议采集数据，去除从重复码，连续采集到 //
// 150ms高电平就结束；非NEC协议则写满FIFO或者连续 //
// 采集到150ms高电平就结束。 //
// 本模块实现采集和编码红外数据，把数据写入BRAM。 //
// data = {ir_in0,ir2_eop,cnt} //
// ir_in0 : 电平状态 //
// ir2_eop: 结束信号 //
// cnt : 电平持续时间 //
// num_cnt : 写入BRAM的红外数据个数，CPU根据这个 //
// 值读取数据 //
//BRAM:位宽32bit //
// 深度1024 //
//如果红外数据很长，BRAM写满之后，后面的红外数据 //
//则无效，不会写入BRAM中。 //
//================================================//
module capture_ir(
input clk , //50MHz
input rst_n , //复位
input ir_in , //1bit红外数据输入
input clean_irq , //CPU清除中断使能
input clean_num , //CPU传过来的清除红外数据个数脉冲信号
//BRAM B端口 用于PL端把数据写入BRAM
output wire ram_rst , //BRAM复位信号,高电平有效
output wire ram_clk , //BRAM时钟
output reg ram_en , //BRAM使能信号
output reg [3:0] ram_we , //BRAM的读写控制信号
output reg [31:0] ram_addr , //BRAM的读写地址
output reg [31:0] ram_wdata , //BRAM的写数据
input [31:0] ram_rdata , //从RAM中读出的数据
output reg irq
);
reg ir_in0 ;
reg ir_in1 ;
reg ir_in2 ;
wire ir2_neg ;
wire ir2_pos ;
wire ir2_sop ;
wire ir2_eop ;
wire flag_eop1;
wire flag_eop2;
reg key_enable;
reg [29:0] cnt_key ;
reg ir2_vld ;
reg [29:0] cnt ;
reg ir2_eop0 ;
reg capture_finish;
reg [31:0] cnt_addr ;
reg [31:0] cnt_num ;
//reg [31:0] num ;
wire write_bram_vld;
reg cpu_rbram ;
reg flag_9ms ;
reg flag_4_5ms ;
reg flag_NEC ;
//NEC 9ms (8-10ms都认为是9ms)
parameter high_8ms = 30'd400_000-1 ; //50M clk
parameter high_10ms = 30'd500_000-1 ; //50M clk
//NEC 4.5ms(4-5ms都认为是4.5ms)
parameter high_4ms = 30'd200_000-1 ; //50M clk
parameter high_5ms = 30'd250_000-1 ; //50M clk
//松手条件,连续110ms的高电平就认为是松开按键
parameter key_end = 30'd5_500_000-1 ; //50M clk
parameter high_30ms = 30'd1_500_000-1 ; //50M clk
//===================================================//
// PL端采集红外数据逻辑 //
//===================================================//
assign ram_rst = 1'b0;
assign ram_clk = clk ;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
ir_in0 <= 1'b0 ;
ir_in1 <= 1'b0 ;
ir_in2 <= 1'b0 ;
end
else begin
ir_in0 <= ir_in ;
ir_in1 <= ir_in0 ;
ir_in2 <= ir_in1 ;
end
end
assign ir2_neg = (ir_in1==1'b0) && ir_in2 && key_enable;
assign ir2_pos = ir_in2==0 && ir_in1 && key_enable;
//IP采集红外数据开始
//非IP清除地址0数据阶段，非CPU读BRAM阶段，非IP写BRAM阶段
assign ir2_sop =(~cpu_rbram)&& (~key_enable) && (ir_in1==1'b0) && ir_in2 ;
//IP采集红外数据结束，连续采集到30ms高电平就结束
assign ir2_eop = flag_eop1 ||flag_eop2;
//非NEC协议，连续采集到30ms高电平或者FIFO满了就结束
assign flag_eop1= ir2_vld && (!flag_NEC) &&((ir_in2 && cnt== high_30ms)||((ram_addr[31:2]==30'd127)&&(ir2_neg||ir2_pos))) ;
//NEC协议就采集33*2+1个数据，后面的重复码不要了,
assign flag_eop2= ir2_vld && flag_NEC &&(cnt_num==32'd66 && ir2_pos) ;
//按键按下阶段
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
key_enable <= 1'b0 ;
end
else if(ir2_sop)begin
key_enable <= 1'b1 ;
end
else if(ir_in2 && cnt_key==key_end)begin
key_enable <= 1'b0 ;
end
end
//松手计数器
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt_key <= 30'b0;
end
else if(key_enable)begin //遇到电平跳转时计数器都清零，
if( (cnt_key==key_end)|| ir2_neg || ir2_pos)
cnt_key <= 30'b0;
else
cnt_key <= cnt_key + 1;
end
end
//电平计数器加1条件
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
ir2_vld <= 1'b0 ;
end
else if(ir2_sop)begin
ir2_vld <= 1'b1 ;
end
else if(ir2_eop)begin
ir2_vld <= 1'b0 ;
end
end
//电平持续时间计数器
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 30'b0;
end
else if(ir2_vld)begin //在计数有效区间内，遇到电平跳转时计数器都清零
if(ir2_eop || ir2_neg || ir2_pos)
cnt <= 30'b0;
else
cnt <= cnt + 1;
end
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
ir2_eop0 <= 1'b0 ;
end
else begin
ir2_eop0 <= ir2_eop ;
end
end
//采集完成信号
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
capture_finish <= 1'b0 ;
end
else if(ir2_eop0)begin
capture_finish <= 1'b1 ;
end
else begin
capture_finish <= 1'b0 ;
end
end
//BRAM的写地址计数器
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
cnt_addr <= 32'd4 ;
end
else if(ir2_vld && (!ir2_eop)&&(ir2_neg || ir2_pos))begin
cnt_addr <= cnt_addr+4 ;
end
else if(ir2_vld && ir2_eop)begin
cnt_addr <= 32'b0 ;
end
else if(ir2_eop0)begin //IP采集完成之后BRAM写地址归1
cnt_addr <= 32'd4 ;
end
end
//统计需要写入的数据个数
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
cnt_num <= 32'b0 ;
end
else if(ir2_vld && (ir2_neg || ir2_pos || ir2_eop))begin
cnt_num <= cnt_num+1 ;
end
else if(ir2_eop0)begin
cnt_num <= 32'b0 ;
end
end
/*
//统计需要写入的数据个数
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
num <= 32'b0 ;
end
else if(ir2_eop)begin
num <= cnt_addr ;
end
else begin
num <= 32'b0 ;
end
end
*/
//BRAM写有效
assign write_bram_vld = ir2_vld || ir2_eop0;
//BRAM写数据端接口信号
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
ram_en <= 1'b0 ;
ram_we <= 4'h0 ;
ram_wdata <= 32'b0;
ram_addr <= 32'b0;
end
else if(write_bram_vld )begin //IP写BRAM的操作
if( ir2_neg || ir2_pos || ir2_eop)begin
ram_en <= 1'b1 ;
ram_we <= 4'hf ; //写入采集到的数据
ram_wdata <= {ir_in2,ir2_eop,cnt}; //{电平状态，结束信号，电平持续时间}
ram_addr <= cnt_addr;
end
else if(ir2_eop0)begin //在BRAM的地址0写入采集到的数据个数
ram_en <= 1'b1 ;
ram_we <= 4'hf ;
ram_wdata <= cnt_num ; //num[31:2]
ram_addr <= cnt_addr;
end
else begin //在BRAM的地址0写入采集到的数据个数
ram_en <= 1'b0 ;
ram_we <= 4'h0 ;
ram_wdata <= 32'b0;
// ram_addr <= 32'b0;
end
end
else if(clean_num)begin //IP清除地址0缓存数据操作
ram_en <= 1'b1 ;
ram_we <= 4'hf ;
ram_wdata <= 32'b0;
ram_addr <= 32'b0;
end
else begin
ram_en <= 1'b0 ;
ram_we <= 4'h0 ;
ram_wdata <= 32'b0;
ram_addr <= cnt_addr;
end
end
//等待CPU读取BRAM阶段
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
cpu_rbram <= 1'b0;
end
else if(capture_finish)begin
cpu_rbram <= 1'b1;
end
else if(clean_num)begin
cpu_rbram <= 1'b0;
end
end
//====================================================//
// 判断红外协议是否是NEC协议逻辑 //
//====================================================//
//判断第一个数据是否为9ms，8-9ms都认为是9ms
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
flag_9ms <= 1'b0;
end
else if(cnt_num==0 && ir2_vld && ir2_pos && (cnt>high_8ms && cnt<high_10ms))begin
flag_9ms <= 1'b1;
end
else if(capture_finish)begin
flag_9ms <= 1'b0;
end
end
//判断第二个数据是否为4.5ms，4-5ms都认为是4.5ms
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
flag_4_5ms <= 1'b0;
end
else if(cnt_num==1 && ir2_vld && ir2_neg && (cnt>high_4ms && cnt<high_5ms))begin
flag_4_5ms <= 1'b1;
end
else if(capture_finish)begin
flag_4_5ms <= 1'b0;
end
end
//协议判断为NEC协议
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
flag_NEC <= 1'b0;
end
else if(flag_4_5ms && flag_9ms )begin
flag_NEC <= 1'b1;
end
else if(cnt_key==key_end)begin //capture_finish
flag_NEC <= 1'b0;
end
end
//====================================================//
// 中断请求逻辑 //
//====================================================//
//中断信号持续2us
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
irq <= 1'b0 ;
end
else if(capture_finish)begin
irq <= 1'b1 ;
end
else if(clean_irq)begin
irq <= 1'b0 ;
end
end
endmodule
下面连个模块是Xilinx自己生成的
`timescale 1 ns / 1 ps
module pl_write_bram2_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input wire ir_in ,
output wire ram_rst ,
output wire ram_clk ,
output wire ram_en ,
output wire [3:0] ram_we ,
output wire [31:0] ram_addr ,
output wire [31:0] ram_wdata ,
input wire [31:0] ram_rdata ,
output wire irq ,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
//CPU往寄存器1（中断寄存器）写1，清除中断。实质是IP看到CPU写寄存器1(不管写入的是什么值)，IP就清除中断
assign clean_irq = slv_reg_wren && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]==2'h1 ;
capture_ir capture_ir(
.clk (S_AXI_ACLK ), //50MHz
.rst_n (S_AXI_ARESETN), //复位
.ir_in (ir_in ), //1bit红外数据输入
.clean_irq (clean_irq ),
.clean_num (slv_reg0[0] ), //CPU传过来的清除红外数据个数脉冲信号 input
//BRAM B端口 用于PL端把数据写入BRAM
.ram_rst (ram_rst ), //output RAM复位信号,高电平有效
.ram_clk (ram_clk ), //output RAM时钟
.ram_en (ram_en ), //output RAM使能信号
.ram_we (ram_we ), //output [3:0] RAM的读写控制信号
.ram_addr (ram_addr ), //output [31:0] RAM的读写地址
.ram_wdata (ram_wdata ), //output [31:0] RAM的写数据
.ram_rdata (ram_rdata ), //input [31:0] 从RAM中读出的数据
.irq (irq ) //output reg
);
// User logic ends
endmodule
`timescale 1 ns / 1 ps
module pl_write_bram2_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input wire ir_in ,
output wire ram_rst ,
output wire ram_clk ,
output wire ram_en ,
output wire [3:0] ram_we ,
output wire [31:0] ram_addr ,
output wire [31:0] ram_wdata ,
input wire [31:0] ram_rdata ,
output wire irq ,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
pl_write_bram2_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) pl_write_bram2_v1_0_S00_AXI_inst (
.ir_in (ir_in ),
.ram_rst (ram_rst ),
.ram_clk (ram_clk ),
.ram_en (ram_en ),
.ram_we (ram_we ),
.ram_addr (ram_addr ),
.ram_wdata (ram_wdata),
.ram_rdata (ram_rdata),
.irq (irq ),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
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