代码
module t_1011(reset,clk,x,z,now,next);
input reset,clk,x;
output z;
output[2:1] now,next;
parameter y0=2'b00,y1=2'b01,y2=2'b11,y3=2'b10;
reg z;
reg[2:1] now,next;
always @ (x or now)
case(now)
y0:if(x)
begin
next=y1;z=0;
end
else
begin
next=y0;z=0;
end
y1:if(x)
begin
next=y1;z=0;
end
else
begin
next=y2;z=0;
end
y2:if(x)
begin
next=y3;z=0;
end
else
begin
next=y0;z=0;
end
y3:if(x)
begin
next=y0;z=1;
end
else
begin
next=y2;z=0;
end
default: begin
next=y0;z=0;
end
endcase
always @ (posedge clk)
begin
if(!reset) now<=y0;
else now<=next;
end
endmodule
说明
无