经典三段式状态机写法

用可综合的verilog模块设计复杂的多输出状态机时常用的方法

module fsm(Clock, Reset ,A, K2, K1);
	input Clock, Reset, A;
	output K2, K1;
	reg	K2, K1;
	reg[1:0] state, nextstate;

parameter
	Idle = 2'b00,
	Start = 2'b01;
	Stop = 2'b10;
	Clear = 2'b11;

//每一个时钟沿可产生一次可能的状态变化
always@(posedge Clock)
	if(!Reset)
		state <= Idle;
	else
		state <= nextstate;

//描述下一状态的组合逻辑
always@(state or A)
	case (state)
		Idle : if(A)	
				nextstate = Start;
				else
				nextstate = Idle;
		Start : if(!A)
				nextstate = Stop;
				else
				nextstate = Start;
		Stop : if(A)
				nextstate = Clear;
				else
				nextstate = Stop;
		Clear : if(!A)	
				nextstate = Idle;
				else
				nextstate = Clear;
		default : nextstate  = 2'bxx;
	endcase

//产生输出K1的组合逻辑
always@(state or Reset or A)
	if(!Reset)
		K1 = 0;
	else
		if(state == Clear && !A)
			K1 = 1;
		else 
			K1 = 0;
	
//产生输出K2的组合逻辑
always@(state or Reset or A)
	if(!Reset)
		K1 = 0;
	else
		if(state == Stop && A)
			K2 = 1;
		else 
			K2 = 0;

endmodule