//1反相器设计;
'timescale 1ns/10ps
module inv(A,Y);
input A;
input Y;
assign Y=~A;
endmodule
//testbench
module inv_tb;
reg aa;
wire yy;
inv inv(
.A(aa),
.Y(yy)
);
initial begin
aa<=0;
#10 aa<=1;
#10 aa<=0;
#10 aa<=1;
end
endmodule
若为8位反相器
则
input [7:0] A;
input [7:0] Y;
//2与非门
module nand_gate(A,B,Y)
input A;
input B;
output Y;
assign Y=~(A&B);
endmodule