VerilogHDL学习笔记4

//最简单的状态机，三角波发生器；
timescale 1ns/10/ps
module tri_gen(clk,res,d_out);
input clk;
input res;
output[8:0] d_out;
reg state;//主状态机寄存器；
reg[8:0] d_out;

always@(posedge clk or negedge res)
if(~res)begin
	state<=0;d_out<=0;
end
else begin
	case(state)
	0:begin d_out<=d_out+1;//上升;
		if(d_out==299)begin
			state<=1;
		end
	end
	1:begin d_out<=d_out-1;//下降；
		if(d_out==1)begin
			state<=0;
		end
	end
end

endmodule