Verilog语法练习：HDL Bits做题笔记（3.1Circuits Combinational Logic）

3、Arithmetic Circuits

目录

3、Arithmetic Circuits

3.1、Half adder

3.2、Full adder

3.3、3-bit binary adder

3.4、Adder

3.5、Signed addition overflow

3.6、100-bit binary adder

3.7、4 digit BCD adder

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3.1、Half adder

problem statement:

Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

solution:

module top_module( 
    input a, b,
    output cout, sum );
    assign {cout,sum}=a+b;
endmodule

3.2、Full adder

problem statement:

Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out. 

solution:

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign {cout,sum}=a+b+cin;
endmodule

3.3、3-bit binary adder

problem statement:

Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[2] is the final carry-out from the last full adder, and is the carry-out you usually see. 

 solution:

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
	
    assign {cout[0],sum[0]}=a[0]+b[0]+cin;
    integer i;
    always@(*)
        for(i=1;i<=2;i++)
    {cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
endmodule

3.4、Adder

problem statement:

 

 

solution:

module FA(input x,y,cin,
          output cout,sum);
    assign {cout,sum}=x+y+cin;
endmodule



module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    wire [3:0] cout;
	generate
	genvar i;
        FA FA0(x[0],y[0],0,cout[0],sum[0]);
        for(i=1;i<=3;i++) begin:adder
            FA FAi(x[i],y[i],cout[i-1],cout[i],sum[i]);
        end
            endgenerate
            assign sum[4]=cout[3];
endmodule

3.5、Signed addition overflow

problem statement:

Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred. 

solution:

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); //
    assign s=a+b;
    assign overflow=((~(a[7]^b[7]))&(b[7]^s[7]))?1:0;
    // assign s = ...
    // assign overflow = ...

endmodule

3.6、100-bit binary adder

problem statement:

Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out. 

solution:

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    assign {cout,sum}=a+b+cin;
endmodule

3.7、4 digit BCD adder

problem statement:

You are provided with a BCD (binary-coded decimal) one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd {
    input [3:0] a,
    input [3:0] b,
    input     cin,
    output   cout,
    output [3:0] sum );

Instantiate 4 copies of bcd_fadd to create a 4-digit BCD ripple-carry adder. Your adder should add two 4-digit BCD numbers (packed into 16-bit vectors) and a carry-in to produce a 4-digit sum and carry out.

 

solution:

module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    wire [3:0] coutadder;

	generate
        genvar i;
        bcd_fadd bcd_fadd0(a[3:0],b[3:0],cin,coutadder[0],sum[3:0]);
        for(i=1;i<=3;i++)
            begin:adder
                bcd_fadd bcd_faddi(a[4*i+3:4*i],b[4*i+3:4*i],coutadder[i-1],coutadder[i],sum[4*i+3:4*i]);
            end
        endgenerate
    assign cout=coutadder[3];
endmodule