Verilog 语法练习：HDL Bits做题笔记（3.1Circuits Combinational Logic）

4、Karnaugh Map to Circuit

目录

4、Karnaugh Map to Circuit

4.1、3-variable

4.2、4-variable

4.3、4-variable

4.4、4-variable

4.5、Minimum SOP and POS

4.6、Karnaugh map

4.7 、Karnaugh map

4.8、K-map implemented with a multiplexer

---

4.1、3-variable

problem statement:

Implement the circuit described by the Karnaugh map below.

Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circu 

solution:

module top_module(
    input a,
    input b,
    input c,
    output out  ); 
    always@(*)
        if(a|b|c)
            out=1;
    else
        out=0;
    
endmodule

4.2、4-variable

problem statement:

Implement the circuit described by the Karnaugh map below.

 

Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.

 

solution:

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out=(a|b|(~c)|(~d))&((~b)|c|(~d))&((~a)|(~b)|d)&((~a)|(~c)|d);
endmodule

4.3、4-variable

problem statement:
 

 

solution:

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    assign out=a|((~b)&c);
        
endmodule

4.4、4-variable

problem statement:

 

 

solution:

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    wire [3:0] e;
    assign e={a,b,c,d};
always@*
    case(e)
        4'b0100:out=1;
        4'b1000:out=1;
        4'b0001:out=1;
        4'b1101:out=1;
        4'b0111:out=1;
        4'b1011:out=1;
        4'b0010:out=1;
        4'b1110:out=1;
        default:out=0;
    endcase
endmodule

4.5、Minimum SOP and POS

problem statement:

A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.

Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.

 

solution:

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 
    assign out_sop=(c&d)|(~a&~b&c);
    assign out_pos=c&(~a|d)&(a|~b|d);
endmodule

4.6、Karnaugh map

problem statement:

 

 

solution:

module top_module (
    input [4:1] x, 
    output f );
    assign f=(x[2]&x[4])|(~x[1]&x[3]);
endmodule

4.7 、Karnaugh map

problem statement:

 

 solution:

module top_module (
    input [4:1] x,
    output f
); 
    assign f=(~x[2]|x[3])&(x[3]|~x[4])&(~x[1]|x[2]|~x[4])&(~x[1]|~x[2]|x[4]);
endmodule

4.8、K-map implemented with a multiplexer

problem statement:

For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.

You are implementing just the portion labelled top_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.

(The requirement to use only 2-to-1 multiplexers exists because the original exam question also wanted to test logic function simplification using K-maps and how to synthesize logic functions using only multiplexers with constant inputs. If you wish to treat this as purely a Verilog exercise, you may ignore this constraint and write the module any way you wish.) 

 

solution:

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    assign mux_in[0]=c?1:(d?1:0);
    assign mux_in[1]=1'b0;
    assign mux_in[2]=d?0:1;
    assign mux_in[3]=c?(d?1:0):0;
    //：题目要求我们在不使用逻辑门的情况下实现顶层模块，我们需要根据卡诺图来看，大概思路就是ab取值固定时，看cd如何变化，也就是把卡诺图当成4列来看
    
endmodule