Verilog语法练习：HDL Bits做题笔记（第二章Verilog language）

2.5、More Verilog Features

目录

2.5、More Verilog Features

2.5.1、Conditional ternary operator

2.5.2、Reduction operators

2.5.3、Reduction:Even wider gates

 2.5.4、Combinational for loop:Vector reversal 2

2.5.5、Combinational for loop:255 bit population count:

2.5.6、Generate for loop:100 bit binary adder 2

2.5.7、Generate for loop :100 digit BCD adder

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2.5.1、Conditional ternary operator

problem statement:

    Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit. You'll probably want some wire vectors for the intermediate results.

solution:

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    // assign intermediate_result1 = compare? true: false;
    
    wire [7:0] f,f1,f2;
    assign f=(a>b)?b:a;
    assign f1=(f>c)?c:f;
    assign f2=(f1>d)?d:f1;
    assign min=f2;
endmodule

2.5.2、Reduction operators

problem statement:

 Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.

 solution:

module top_module (
    input [7:0] in,
    output parity); 
assign parity=^in;
endmodule

注：

 

 

2.5.3、Reduction:Even wider gates

problem statement:

Build a combinational circuit with 100 inputs, in[99:0].

There are 3 outputs:

• out_and: output of a 100-input AND gate.
• out_or: output of a 100-input OR gate.
• out_xor: output of a 100-input XOR gate.

solution:

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
assign out_and=∈
assign out_or=|in;
assign out_xor=^in;
endmodule

 2.5.4、Combinational for loop:Vector reversal 2

problem statement:

Given a 100-bit input vector [99:0], reverse its bit ordering.

solution:

module top_module( 
    input [99:0] in,
    output [99:0] out
);
integer i;
    always@(*) begin
    for(i=99;i>=0;i--)
         out[i]=in[99-i];
    end
endmodule

2.5.5、Combinational for loop:255 bit population count:

problem statement:

A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector. 

solution:

module top_module( 
    input [254:0] in,
    output [7:0] out );
    

    integer i;
    always@(*) begin
        out=0;
        for(i=0;i<=254;i++) 
            if(in[i]==1)
                out=out+1;
            else
                out=out;
       
    end
endmodule

2.5.6、Generate for loop:100 bit binary adder 2

problem statement;

 Create a 100-bit binary ripple-carry adder by instantiating 100 full adders. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[99] is the final carry-out from the last full adder, and is the carry-out you usually see.

 solution:

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    assign {cout[0],sum[0]}=a[0]+b[0]+cin;
    integer i;
    always@*
    for(i=1;i<=99;i++)
    {cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
endmodule

2.5.7、Generate for loop :100 digit BCD adder

problem statement:

 

You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd {
    input [3:0] a,
    input [3:0] b,
    input     cin,
    output   cout,
    output [3:0] sum );

Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.

solution:

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    wire[99:0] cout1;
    generate 
    genvar i;
   
        for(i=0;i<=99;i++) begin:addr
            if(i == 0) begin
                bcd_fadd bcd_fadd0(a[3:0],b[3:0],cin,cout1[0],sum[3:0]);         
            end
                else
               begin 
                   bcd_fadd bcd_faddi(a[4*i+3:4*i],b[4*i+3:4*i],cout1[i-1],cout1[i],sum[4*i+3:4*i]);        
                   end
        end
            assign cout=cout1[99];
    endgenerate
endmodul

 注：重复调用模块需要使用关键字generate.循环begin后面需要加循环名称，循环变量定义为genvar。