Verilog 语法练习：HDL Bits做题笔记（3.2 Circuits Sequential Logic )

目录

1、Lateches and Flip-Flops

1.1、D flip-flop

1.2、D flip-flops

1.3、 DFF with reset

1.4、DFF with reset value

1.5、DFF with asynchronous reset

1.6、DFF with byte enable

1.7、 D Latch

1.8、DFF

1.9、DFF 

1.10、DFF + gate

1.11、Mux and DFF

1.12、Mux and DFF

1.13、DFF and gates

1.14、 Create circuit from truth table

1.15、Detect an edge

1.16、Detect both edges

1.17、Edge capture register

1.18、Dual-edge triggered flip-flop

---

1、Lateches and Flip-Flops

1.1、D flip-flop

problem statement:

A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal.

 

D flip-flops are created by the logic synthesizer when a clocked always block is used (See alwaysblock2). A D flip-flop is the simplest form of "blob of combinational logic followed by a flip-flop" where the combinational logic portion is just a wire.

Create a single D flip-flop.

solution:

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always @(posedge clk)
        q=d;
    
endmodule

1.2、D flip-flops

problem statement:

Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk. 

solution:

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk)
        q=d;
    
endmodule

1.3、 DFF with reset

problem statement:

Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk. 

solution:

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk )
        if(  reset)
            q<=2'h00;
    else
        q<=d;
endmodule

1.4、DFF with reset value

problem statement:

Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk. 

solution:

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
 
    always@(negedge clk)
        if(reset)
            q<='h34;
    else
        q<=d;
endmodule

1.5、DFF with asynchronous reset

problem statement:

Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk. 

solution:

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset)
        if(areset)
            q=0;
    else
        q=d;
endmodule

1.6、DFF with byte enable

problem statement:

Create 16 D flip-flops. It's sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].

resetn is a synchronous, active-low reset.

All DFFs should be triggered by the positive edge of clk.

 

solution:

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk) begin
        if(!resetn)
            q=0;
    else begin
        case(byteena)
            2'b01:q[7:0]=d[7:0];
            2'b11:q=d;
            2'b10:q[15:8]={{d[15]},{d[14]},{d[13]},{d[12]},{d[11]},{d[10]},{d[9]},{d[8]}};
            default:q=q;
        endcase
    end
    end
endmodule

1.7、 D Latch

problem statement:

Implement the following circuit:

Note that this is a latch, so a Quartus warning about having inferred a latch is expected. 

solution:

module top_module (
    input d, 
    input ena,
    output q);
    always@(*)
        if(ena)
            q<=d;
    else
        q<=q;
endmodule

1.8、DFF

problem statement:

Implement the following circuit:

 

 

solution:

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset异步复位
    output q);
    always@(posedge clk or posedge ar)
        if(ar)
            q=0;
    else
        q=d;
endmodule

1.9、DFF 

problem statement:

Implement the following circuit:

 

 

 solution:

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset同步复位
    output q);
    always@(posedge clk )
        if(r)
            q=0;
    else
        q=d;
endmodule

1.10、DFF + gate

problem statement:

mplement the following circuit:

 

solution:

module top_module (
    input clk,
    input in, 
    output out);
wire w1;
    assign w1=in^out;
    always@(posedge clk) begin
        out<=w1;
       
    end
endmodule

1.11、Mux and DFF

problem statement:

 

Taken from ECE253 2015 midterm question 5

Consider the sequential circuit below:

 

Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.

solution:

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    wire q;
    always@(*) begin
        case(L)
            0:q=q_in;
            1:q=r_in;
            default:q=q; 
        endcase
    end
    always@(posedge clk)
                Q<=q;
endmodule

1.12、Mux and DFF

problem statement:

Consider the n-bit shift register circuit shown below:

 

Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.

 

solution:

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    wire w1,d;
        always@(*) begin
            case(E)
                0:w1=Q;
                1:w1=w;
                default:w1=w1;
            endcase
        end
        always@(*) begin
            case(L)
                0:d=w1;
                1:d=R;
                default:d=d;
            endcase
        end
            always@(posedge clk)
                Q=d;
endmodule

1.13、DFF and gates

problem statement:

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.

 

 

solution:

module top_module (
    input clk,
    input x,
    output z
); 
wire  d1,d2,d3;
    reg Q1,Q2,Q3;

    always@(*) begin
        d1<=x^Q1;
        d2<=x&(~Q2);
        d3<=x|(~Q3);
    end
        always@(posedge clk) begin
            Q1<=d1;
            Q2<=d2;
            Q3<=d3;
         
        end
     assign  z=!(Q1|Q2|Q3);
endmodule

1.14、 Create circuit from truth table

problem statement:

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

J	K	Q
0	0	Qold
0	1	0
1	0	1
1	1	~Qold

solution:

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    always@(posedge clk)
        case({j,k})
            2'b00:Q=Q;
            2'b01:Q=0;
            2'b10:Q=1;
            default:Q=~Q;
           
        endcase
endmodule

1.15、Detect an edge

problem statement:

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

 

solution:

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] d;
    always@(posedge clk) begin
        d <= in;
        pedge<= (~d)&in;
    end
endmodule

1.16、Detect both edges

problem statement:

For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and anyedge[1] are shown separately

 

 

solution:

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0] w;
    always@(posedge clk) begin
        w<=in;
    anyedge<=w^in;
    end
endmodule

1.17、Edge capture register

problem statement:

For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the 'reset' event occurs one cycle earlier than the 'set' event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

 

solution:

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] reg_in;
    wire [31:0] nedge;
    
    always@(posedge clk) begin
       nedge=reg_in&~in;
        reg_in<=in;//pre
         
        if(reset)
            out<=0;
        else if(nedge!=0)
            out<=nedge|out;
        else
            out<=out;
    end
endmodule

1.18、Dual-edge triggered flip-flop

problem statement:

You're familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

Build a circuit that functionally behaves like a dual-edge triggered flip-flop:

 

 

solution:

module top_module (
    input clk,
    input d,
    output q
);
    reg q1,q2;
    always@(posedge clk)
        q1<=d^q2;
    always@(negedge clk)
        q2<=d^q1;
    assign q=q1^q2;
endmodule