Verilog 语法练习：HDL Bits语法笔记（第二章 Verilog language）

2.3、Modules:Hierarchy

目录

2.3、Modules:Hierarchy

2.3.1、Modules

2.3.2、Connecting ports by position

2.3.3、Connecting ports by name

2.3.4、Three modules

2.3.5、Modules and vectors

2.3.5、Adder 1

2.3.6、Adder2

2.3.7、Carry-select adder 

2.3.8、Adder-subtractor

---

2.3.1、Modules

problem statement:

 模块调用：通过位置 通过信号名称

solution:

module top_module ( input a, input b, output out );
    mod_a mod1(
        .in1(a),
        .in2(b),
        .out(out));
endmodule
module top_module ( input a, input b, output out );
    mod_a mod1(a,b,out);
endmodule

注：两种方法都可以，实现模块调用 

2.3.2、Connecting ports by position

problem statement:

 

 被调用模块：

 

solution：

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a mod1(out1,out2,a,b,c,d);
endmodule

2.3.3、Connecting ports by name

problem statement:

 

 

 

 

solution:

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a(
        .out1(out1),
        .out2(out2),
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d));
endmodule

2.3.4、Three modules

problem statement:

You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.

The module provided to you is: module my_dff ( input clk, input d, output q );

Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

 

 

solution:

module top_module ( input clk, input d, output q );
wire w1,w2;
    my_dff dff1(
        .clk(clk),
        .d(d),
        .q(w1));
    my_dff dff2(
        .clk(clk),
        .d(w1),
        .q(w2));
    my_dff dff3(
        .clk(clk),
        .d(w2),
        .q(q));
endmodule

注：需要事先定义两个线网类型变量 对应第一个 第二个my_dff模块的输出q

2.3.5、Modules and vectors

problem statement:

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

 

 

 solution:

module mux4_1(
        input [1:0] sel,
        input[7:0] in0,in1,in2,in3,
        output[7:0] out);
        always@(sel)
            case(sel)
                0:out=in0;
                1:out=in1;
                2:out=in2;
                3:out=in3;
                default:out=in0;
            endcase
                
endmodule
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0]w1,w2,w3;
    my_dff8 dff1(clk,d,w1);
    my_dff8 dff2(clk,w1,w2);
    my_dff8 dff3(clk,w2,w3);
    mux4_1 mux(sel,d,w1,w2,w3,q);
    
endmodule  

注：题目没有给出四选一的数据选择器，需要编写该模块，并在顶层模块中调用。

用三个线网类型变量来连接三个my_dff8模块的输出q 至下一个模块d或者3；

2.3.5、Adder 1

problem statement:

 

 

solution:

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout;
    add16 add1(a[15:0],b[15:0],0,sum[15:0],cout);
    add16 add2(a[31:16],b[31:16],cout,sum[31:16]);
endmodule

2.3.6、Adder2

problem statement:

 

 

solution:

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire cout;
    add16 add1(a[15:0],b[15:0],0,sum[15:0],cout);
    add16 add2(a[31:16],b[31:16],cout,sum[31:16], );
endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );
    assign {cout,sum}=a+b+cin;
// Full adder module here

endmodule

2.3.7、Carry-select adder 

problem statement:

 

 

 

solution:

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire sel;
    wire [15:0] sum1,sum2;
    add16 add1(a[15:0],b[15:0],0,sum[15:0],sel);
    add16 add2(a[31:16],b[31:16],0,sum1, );
    add16 add3(a[31:16],b[31:16],1,sum2, );
    mux2_1 mux(sum1,sum2,sel,sum[31:16]);
endmodule
module mux2_1(input [15:0]a,b,
              input sel,
              output[15:0] out);
    always @(sel)
        case(sel)
            0:out=a;
            1:out=b;
            default:out=a;
        endcase
endmodule

---

注：16位的加法器模块已经给出，需要再设计一个二选一的数据选择器 

2.3.8、Adder-subtractor

problem statement:

 

 

 

 solution:

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire[31:0] b1;
    wire w1;
    always@(*) 
        begin
    if(sub==1'b1)
        b1=~b;
     else
         b1=b;
    	end
    add16 add1(a[15:0],b1[15:0],sub,sum[15:0],w1);
    add16 add2(a[31:16],b1[31:16],w1,sum[31:16], );
endmodule

 注：图中的逻辑门为异或门，根据提示可知，可以根据sub的0 1值判断输出是否取反。