部分参考代码
(末尾附文件)
分频模块的代码如下所示:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SZ is
port(
CLK :in std_logic;
CP :out std_logic
);
end SZ;
ARCHITECTURE ART OF SZ IS
SIGNAL COUNT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK = '1'THEN
COUNT <= COUNT + 1;
END IF;
END PROCESS;
CP<= COUNT(3);
END ART;
控制模块的代码如下图所示:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CTRL is
port(
LEFTT :in std_logic;
RIGTH :in std_logic;
BRAKE :in std_logic;
NIGHT :in std_logic;
LP :out std_logic;
RP :out std_logic;
LR :out std_logic;
NIGHT_LED :out std_logi