Fsm serialdata

题目: https://hdlbits.01xz.net/wiki/Fsm_serialdata

代码：
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //

// Use FSM from Fsm_serial
parameter IDLE = 0, START = 1, DATA_T = 2, STOP = 3, WRONG = 4;
reg [2:0] state, next_state;

always @(posedge clk) begin
    if(reset)
        state <= IDLE;
    else
        state <= next_state;        
end

always @(*) begin
    case(state)
        IDLE   : next_state = !in ? START : IDLE;
        START  : next_state = DATA_T;
        DATA_T : next_state = (cnt < 7) ? DATA_T : (in ? STOP : WRONG);
        STOP   : next_state = in ? IDLE : START;
        WRONG  : next_state = in ? IDLE : WRONG;
        default : next_state = IDLE;
    endcase
end

reg [3:0] cnt;
always @(posedge clk) begin
    if(reset) 
        cnt <= 4'd0;
    else begin
        if(state == START)
            cnt <= 4'd0;
        else
            cnt <= cnt + 1;
    end          
end

//output
assign done = state == STOP;

reg [7:0] data_r;
// New: Datapath to latch input bits.
always @(posedge clk) begin
    if(reset)
        data_r <= 8'd0;
    else begin
        data_r <= (next_state == DATA_T) ? {in, data_r[7:1]} : data_r;       
    end
 end

always @(*) begin
    if(done)
        out_byte <= data_r;
    else
        out_byte <= out_byte;
end

endmodule