Fsm ps2data

题目：https://hdlbits.01xz.net/wiki/Fsm_ps2data

代码：
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output reg [23:0] out_bytes,
output done); //

parameter IDLE = 0, S0 = 1, S1 = 2, S2 = 3;
reg [1:0] state, next_state;
always @(posedge clk) begin
    if(reset)
        state <= IDLE;
    else
        state <= next_state;
end

always@(*) begin
    case(state)
        IDLE : next_state = in[3] ? S0 : IDLE;
          S0 : next_state = S1;
          S1 : next_state = S2;
          S2 : next_state = in[3] ? S0 : IDLE;
    endcase
end

// Output logic
assign done = state == S2;

// New: Datapath to store incoming bytes.
always @(posedge clk) begin
    case(next_state)
    	IDLE :  out_bytes <= 24'd0;
        S0, S1, S2  :  out_bytes <= {out_bytes[15:0], in}; 
    endcase
end

endmodule