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ALU.v

module ALU(

input rst,

input[3:0] alu_ct,

input[31:0] alu_src1,alu_src2,

output alu_zero,

output reg [31:0] alu_res

    );

    assign alu_zero= (alu_res==0)?1:0;

    always@(*)

        if(!rst)begin

            alu_res = 32'b0;

        end

        else begin

            case(alu_ct)

                4'b0010:alu_res = alu_src1 + alu_src2;

                4'b0110:alu_res = alu_src1 - alu_src2;

                default:alu_res = 0;

            endcase

        end

endmodule

 

ALU_tb.v

module ALU_tb();

  reg clk, rst_n;

  initial begin

    clk <= 0;

    rst_n <= 0;

    #7 rst_n <= 1;

  end

  always begin

    #5 clk <= ~clk;

  end

  // generate tick

  integer _tb_tick;

  always @(posedge clk) begin

    if (!rst_n) begin

      _tb_tick <= 0;

    end

    else begin

      _tb_tick <= _tb_tick + 1;

    end

  end

 

  reg[3:0]    alu_ct;

  reg[31:0]   alu_src1, alu_src2;

  wire        alu_zero;

  wire[31:0]  alu_res;

 

  ALU alu(

    .rst      (rst_n),

    .alu_ct   (alu_ct),

    .alu_src1 (alu_src1),

    .alu_src2 (alu_src2),

    .alu_zero (alu_zero),

    .alu_res  (alu_res)

  );

 

  always @(posedge clk) begin

    case (_tb_tick)

      0: begin

        alu_ct    <= 0;

        alu_src1  <= 0;

        alu_src2  <= 0;

      end

      1: begin

        alu_ct    <= 4'b0010;

        alu_src1  <= 32'd12345678;

        alu_src2  <= 32'd11111111;

      end

      2: begin

        alu_ct    <= 4'b0110;

        alu_src1  <= 32'd3322;

        alu_src2  <= 32'd2233;

      end

      3: begin

        alu_ct    <= 4'b0110;

        alu_src1  <= 32'd12345678;

        alu_src2  <= 32'd12345678;

      end

    endcasecounter_test

    if (_tb_tick >= 4) $finish;

  end

 

  initial begin

      $monitor("monitor clk=%b,rst_n=%b,alu_ct=%h:alu_zero=%b,alu_res=%h", clk, rst_n, alu_ct, alu_zero, alu_res);

  end

  initial

  begin

      $dumpfile("ALU_tb.vcd");

      $dumpvars(0,ALU_tb);

  end

 

endmodule

 

ALU.sh

iverilog -o ALU_tb ALU_tb.v ALU.v

vvp -n ALU_tb -lxt2

cp ALU_tb.vcd ALU_tb.lxt

gtkwave ALU_tb.lxt

 

yiwei.v

module yiwei_module (

    input clk,

    input reset,

    input shift_ena,

    input count_ena,

    input data,

    output reg [3:0] q);

 

    initial begin

        q=0;

    end

 

    always@(posedge clk) begin

        if(reset)

            q=0;

        else

        if(shift_ena)

            q <= {q[2:0], data};

        else if(count_ena)

            q <= q - 1'b1;

        else

            q <= q;

    end

   

endmodule

 

yiwei_tb.v

module yiwei();

    reg clk,reset,shift_ena,count_ena,data;

    wire [3:0]q;

 

    initial begin

        reset=1;

        #2 reset=0;

        end

 

    initial begin

        $monitor("monitor clk=%d,reset=%d,shift_ena=%d,count_ena=%d,data=%d:q=%d",clk,reset,shift_ena,count_ena,data,q);

        clk=1;  shift_ena<=0; count_ena<=0;data<=0;

        #2 shift_ena<=1; count_ena<=0;data<=1;

        #1 shift_ena<=1; count_ena<=0;data<=0;

        #2 shift_ena<=1; count_ena<=0;data<=1;

        #1 shift_ena<=0; count_ena<=0;data<=1;

        #3 shift_ena<=0; count_ena<=1;data<=1;

        #5 shift_ena<=0; count_ena<=0;data<=1;

        #5 $finish;

 

    end

 

    always #0.5 clk=~clk;

   

    yiwei_module yiwei_module (

        .clk(clk),

        .reset(reset),

        .shift_ena(shift_ena),

        .count_ena(count_ena),

        .data(data),

        .q(q)

    );

    initial

    begin

        $dumpfile("yiwei.vcd");

        $dumpvars(0,yiwei);

    end

endmodule // yiwei

 

yiwei.sh

iverilog -o yiwei yiwei_tb.v yiwei.v

vvp -n yiwei -lxt2

cp yiwei.vcd yiwei.lxt

gtkwave yiwei.lxt