【Verilog - 组合逻辑 - 基础1】2. 导线与连接
千举万变,其道一也。《荀子·儒效》
1.0 介绍
Verilog的导线是最基本的元件,每个硬件都离不开它。所以基本要练好!
1.1 简单连接
最简单的连接如下:
module xian1(input jia, output yi);
assign yi = jia;
endmodule
可以这样来测试,
//模拟
module xian1(input jia, output yi);
assign yi = jia;
endmodule
//测试
module xian1_tb;
reg jia;
wire yi;
xian1 dut(jia, yi);
initial begin
jia = 0;
#0
$display("jia = %b, yi = %b", jia,yi);
jia = 1;
#0
$display("jia = %b, yi = %b", jia,yi);
$finish;
end
endmodule
结果如下,
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim xian1.v
jia = 0, yi = 0
jia = 1, yi = 1
1.1.1 多个数
以上的电线只是一个单纯的线。如果有多个电线,可以同时的连接如下,
module xian1(input [5:0] jia, output [5:0] yi);
assign yi = jia; //如同yi[0]=jia[0];...;yi[5]=jia[5];
endmodule
可见,assign不需要变,可以同时赋值连接多个导线。
然后,可以这样来测试,
//模拟
module xian1(input [5:0] jia, output [5:0] yi);
assign yi = jia;
endmodule
//测试
module xian1_tb;
reg [5:0] jia;
wire [5:0] yi;
xian1 dut(jia, yi);
integer i;
initial begin
for (i = 0; i < 8; i++) begin
jia = i;
#0
$display("jia = %b, yi = %b", jia,yi);
end
end
endmodule
结果如下,
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim duoxian.v
jia = 000000, yi = 000000
jia = 000001, yi = 000001
jia = 000010, yi = 000010
jia = 000011, yi = 000011
jia = 000100, yi = 000100
jia = 000101, yi = 000101
jia = 000110, yi = 000110
jia = 000111, yi = 000111
1.2 常量的连接
有一些时候,会需要连接常量。这个如同把一个导线永久的设为某个电压。
module qian(output [2:0] bagua);
wire [2:0] qian_gua = 3'b111;
assign bagua = qian_gua;
endmodule
module kun(output [2:0] bagua);
assign bagua = 3'b000;
endmodule
测试如下,
module qian(output [2:0] bagua);
wire [2:0] qian_gua = 3'b111;
assign bagua = qian_gua;
endmodule
module kun(output [2:0] bagua);
assign bagua = 3'b000;
endmodule
module qiankun_ceshi;
wire [2:0] qian_gua, kun_gua;
qian dut1(qian_gua);
kun dut2(kun_gua);
initial begin
$display("qian = %b, kun = %b", qian_gua,kun_gua);
$finish;
end
endmodule
这里,wire 可以视为一个中介,或临时变量。
效果如下,
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim qiankun.v
qian = 111, kun = 000
1.2.1 常量的定义
以上是用二进制来定义的。<长度>'b<数据>
如3'b111
也可以用十进制,十六进制来定义,如下
3'd7
8'h1
1.3 更复杂的连接方法
有一些时候,我们想单独的对导线连接。这时,就可以用{}
和[]
的方法了。
1.3.1 []
连接法
取一部分
//模块
module ren(input [5:0] gua, output [1:0] ren_yao);
assign ren_yao = gua[3:2];
endmodule
//测试
module ren_ceshi;
reg [5:0] gua;
wire [1:0] ren_yao;
ren dut(gua, ren_yao);
initial begin
gua = 6'b001_000;
#0;
$display("gua = %b, ren_yao = %b", gua, ren_yao);
gua = 6'b111_111;
#0;
$display("gua = %b, ren_yao = %b", gua, ren_yao);
gua = 6'b000_000;
#0;
$display("gua = %b, ren_yao = %b", gua, ren_yao);
end
endmodule
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim ren.v
gua = 001000, ren_yao = 10
gua = 111111, ren_yao = 11
gua = 000000, ren_yao = 00
连接一部分
module jiao_hu_gua(input [5:0] jia, output [5:0] yi);
assign yi[2:0] = jia[5:3];
assign yi[5:3] = jia[2:0];
endmodule
module ceshi;
wire [5:0] yi;
reg [5:0] jia;
jiao_hu_gua dut(jia, yi);
initial begin
jia = 6'b010_111;
#0;
$display("jia = %b, yi = %b", jia, yi);
jia = 6'b100_010;
#0;
$display("jia = %b, yi = %b", jia, yi);
$finish;
end
endmodule
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim hu.v
jia = 010111, yi = 111010
jia = 100010, yi = 010100
1.3.2 {}
连接法
取一部分和
module zong_gua(input [5:0] jia, output [5:0] yi);
assign yi = {jia[0], jia[1], jia[2], jia[3], jia[4], jia[5]};
endmodule
连接一部分
module zong_gua(input [5:0] jia, output [5:0] yi);
assign {yi[0], yi[1], yi[2], yi[3],yi[4],yi[5]} = jia;
endmodule
测试代码如下,
module zong_gua(input [5:0] jia, output [5:0] yi);
assign yi = {jia[0], jia[1], jia[2], jia[3], jia[4], jia[5]};
//assign {yi[0], yi[1], yi[2], yi[3],yi[4],yi[5]} = jia;
endmodule
module ceshi;
reg [5:0] jia;
wire [5:0] yi;
zong_gua dut(jia,yi);
initial begin
jia = 6'b100_000;
#0;
$display("jia = %b, yi = %b", jia,yi);
$finish;
end
endmodule
两个的结果都一样,
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim zong.v
jia = 100000, yi = 000001
2.0 注意点~
2.1 模块的命名
有些时后,可能会忘计给一个模块命名。这会导致,
...
reg jia;
wire yi;
xian(jia, yi);
...
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim xian1.v
xian1.v:12: error: Instantiation of module xian1 requires an instance name.
2 error(s) during elaboration.
加个名子就可以了,
...
reg jia;
wire yi;
xian dut(jia, yi);
...
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim xian1.v
jia = 0, yi = 0
jia = 1, yi = 1
2.2 wire
在模块里的用法
之前已经讨论过wire在测试里的用法(输出必连接wire, 输入必连接reg).
在模块里, wire 如同一个中介的变量,或导线。
如,
assign yi[2:0] = jia[5:3];
等于,
wire [2:0] zhong = jia[5:3];
assign yi[2:0] = zhong;
也等于
wire [2:0] zhong;
assign zhong = jia[5:3];
assign yi[2:0] = zhong;
2.3 wire
导线的冲突和落空
如果不小心把两个带不以样的信号线连接了,就会导致冲突。冲突的表现是一个x
的,
liu2333hui@liu2333hui-PC:~/verilog/nihao$ cat maodun.v
module maodun(output jia);
assign jia = 1'b1;
assign jia = 1'b0;
endmodule
module ceshi;
wire jia;
maodun dut(jia);
initial begin
$display("jia = %b", jia);
$finish;
end
endmodule
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim maodun.v
jia = x
同样, 如果没有设一个导线的值,它就会变成一个z
,
liu2333hui@liu2333hui-PC:~/verilog/nihao$ cat kong.v
module kong(output jia);
endmodule
module ceshi;
wire jia;
kong dut(jia);
initial begin
$display("jia = ", jia);
$finish;
end
endmodule
liu2333hui@liu2333hui-PC:~/verilog/nihao$ epicsim kong.v
jia = z