FPGA学习【1】环境安装与验证（流水灯时序）上

环境安装-vivado

按照这个博主的流程一步一步安装就行，全文配合多图，每一步都有图形指导，安装成功率高，关键还提供安装包。

链接: link

第一个Verilog HDL程序

完成流水灯的时钟驱动

创建工程文件，依次按图片来操作

后续会让你添加源文件，但是我们本身没有源文件的添加，所以就直接点击next到下面这张图，

至此，工程创建完毕，接下来创建工程文件。

下面这张图告诉我们提示定义I/O的端口，这里我们可以不定义，当让定义也没问题，点击OK完成所有文件添加

你会看到这样的主界面

双击就能快乐的编辑代码了，在这里我们先不追究代码的含义，其实会汇编和C语言的话也能大概懂一些，往刚才的文件里添加这些代码

//===========================================================================
// Module name: led_test.v
//===========================================================================
`timescale 1ns / 1ps

module led_test 
(             
  sys_clk_p,      // Differentia system clock 200Mhz input on board
  sys_clk_n,
  rst_n,          // reset ,low active            
  led,             // LED,use for control the LED signal on board
  fan_pwm           //fan control
 );
             
//===========================================================================
// PORT declarations
//===========================================================================

input         sys_clk_p;
input         sys_clk_n;
input         rst_n;
output [3:0]  led;
output fan_pwm;
//define the time counter
reg [31:0]   timer;                  
reg [3:0]    led;
assign fan_pwm =1'b0;
//===========================================================================
//Differentia system clock to single end clock
//===========================================================================
wire        sys_clk;
 IBUFGDS u_ibufg_sys_clk   //专用原语，差分信号输入
     (
      .I  (sys_clk_p),            
      .IB (sys_clk_n),          
      .O  (sys_clk  )        
      );          
//===========================================================================
// cycle counter:from 0 to 1 sec
//===========================================================================
  always @(posedge sys_clk or negedge rst_n)    
    begin
      if (~rst_n)                           
          timer <= 32'd0;                     // when the reset signal valid,time counter clearing
      else if (timer == 32'd199_999_999)    //1 seconds count(200M-1=199999999) 系统时钟200Mhz，周期5ns，计数0-199_999_999,共2*10^8个周期
          timer <= 32'd0;                       //count done,clearing the time counter
      else
		    timer <= timer + 1'b1;            //timer counter = timer counter + 1，每周期上升沿计数
    end

//===========================================================================
// LED control
//===========================================================================
  always @(posedge sys_clk or negedge rst_n)   
    begin
      if (~rst_n)                      
          led <= 4'b0000;                  //when the reset signal active         
      else if (timer == 32'd49_999_999)    //time counter count to 0.25 sec,LED1 lighten
    
          led <= 4'b0001;                 
      else if (timer == 32'd99_999_999)    //time counter count to 0.5 sec,LED2 lighten
      begin
          led <= 4'b0010;                  
        end
      else if (timer == 32'd149_999_999)   //time counter count to 0.75 sec,LED3 lighten
          led <= 4'b0100;                                          
      else if (timer == 32'd199_999_999)   //time counter count to 1 sec,LED4 lighten
          led <= 4'b1000;                         
    end
    
endmodule

然后创建管脚约束文件xdc文件

与之前步骤相同但是略有区别



双击并添加下面代码

############## clock define##################
create_clock -period 5.000 [get_ports sys_clk_p]
set_property PACKAGE_PIN AE10 [get_ports sys_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
############## key define##################
set_property PACKAGE_PIN AG27 [get_ports rst_n]
set_property IOSTANDARD LVCMOS25 [get_ports rst_n]
#################fan define##################
set_property IOSTANDARD LVCMOS25 [get_ports fan_pwm]
set_property PACKAGE_PIN AE26 [get_ports fan_pwm]
##############LED define##################
set_property PACKAGE_PIN A22 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]

set_property PACKAGE_PIN C19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]

set_property PACKAGE_PIN B19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]

set_property PACKAGE_PIN E18 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
#############SPI Configurate Setting##################
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

记住保存所有的文件