HDLbits--Exams/review2015 fsmseq

简单的状态机

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    
    parameter b1=0,b2=1,b3=2,b4=3,ss=4;
    reg [2:0] state,next_state;
    
    always@(*)
        begin
            case(state)
                b1:
                    next_state<=data?b2:b1;
                b2:
                    next_state<=data?b3:b1;
                b3:
                    next_state<=data?b3:b4;
                b4:
                    next_state<=data?ss:b1;
                ss:
                    next_state<=ss;

            endcase
        end
    always@(posedge clk)
        begin
            if(reset)
                state<=b1;
            else
                state<=next_state;
        end
    
    assign start_shifting=state==ss;

endmodule