https://hdlbits.01xz.net/wiki/Exams/review2015_fsmseq
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting);
parameter S0=0,S1=1,S2=2,S3=3,S4=4;
reg [2:0] cs,ns;
always @(*)
begin
case (cs)
S0:ns=data?S1:S0;
S1:ns=data?S2:S0;
S2:ns=data?S2:S3;
S3:ns=data?S4:S0;
S4:ns=data?S4:S4;
endcase
end
always @(posedge clk)
begin
if (reset)
cs<=S0;
else
cs<=ns;
end
assign start_shifting= (cs==S4);
endmodule