Exams/review2015 fsmshift

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);

    reg [1:0]counter;
    always@(posedge clk) begin
        if(reset) begin
            counter<=0;
            shift_ena<=1'b1;
        end
        else if(shift_ena) begin
            	if(counter==3) begin
           		shift_ena<=0;
            	counter<=0;
        	end	
            else begin
           	 	counter<=counter+1;
            	shift_ena<=shift_ena;
            end
        end
    end
endmodule