Verilog[二进制码转格雷码功能仿真]

• 二进制码转格雷码

//Bin_to_Gray.v
module Bin_to_Gray 
#(
    parameter NUM = 4
)
(
    input [NUM-1:0] bin,
    output [NUM-1:0] gray
);
        
    assign gray = (bin >> 1) ^ (bin); 

endmodule

• 二进制码转格雷码仿真测试testbench

//Bin_to_Gray_tb.v

`timescale 1ns/1ps

module Bin_to_Gray_tb();
    parameter num = 4;
    
    reg [num-1:0] bin_in;
    wire [num-1:0] gray_out;

    Bin_to_Gray #(.NUM(num))
                bin2gray(
                        .bin(bin_in),
                        .gray(gray_out)
                        );

    integer i = 0;
    initial begin
        for(i = 0;i < 16;i = i + 1) begin
            bin_in = i;
            #10;
        end
    end 

endmodule

• 仿真结果