代码: 三段式状态机
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
case(state)
B:
if(in==0)begin
next_state=A;
end
else begin
next_state=B;
end
A:
if(in==0)begin
next_state=B;
end
else begin
next_state=A;
end
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
if(areset)begin
state<=B;
end
else begin
state<=next_state;
end// State flip-flops with asynchronous reset
end
// Output logic
// assign out = (state == ...);
assign out=(state==B);
endmodule