module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
// FSM from fsm_ps2
reg [23:0]shift;
reg[3:0] state,next_state;
parameter get_0=4'b0001,get_1=4'b0010,get_wait2=4'b0100,get_wait3=4'b1000;
// State transition logic (combinational)
always@(*)begin
case(state)
get_0:
if(in[3]==1)
next_state<=get_1;
else
next_state<=get_0;
get_1:
next_state<=get_wait2;
get_wait2:
next_state<=get_wait3;
get_wait3:
if(in[3]==1)
next_state<=get_1;
else
next_state<=get_0;
endcase
end
// State flip-flops (sequential)
always@(posedge clk)
if(reset)
state<=get_0;
else
state<=next_state;
// Output logic
assign done=state==get_wait3;
always@(posedge clk)
if(reset)
out_bytes<=24'b0;
else
out_bytes<={out_bytes[15:0],in};
endmodule